| // =============================================== |
| // Copyright 2011, Cypress Semiconductor Corporation. |
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| // =============================================== |
| // File : $File: //depot/icm/proj/s8fmlt/icmrel/ipVault/opus/s8fmlt/s8fmlt_eqcoldel/behavioral/verilog.v $ |
| // Author : ixi |
| // Date : August 15, 2011 |
| // $Revision: 1 $ |
| // =============================================== |
| // // Description: |
| |
| `timescale 1ns/1ps |
| |
| |
| module s8fmlt_eqcoldel (out, in, vgnd, vnb, vpb, vpwr); |
| output out; |
| input in; |
| input vgnd; |
| input vnb; |
| input vpb; |
| input vpwr; |
| wire supply_ok =(vnb===1'b0) & (vgnd===1'b0) & (vpb===1'b1) & (vpwr===1'b1); |
| |
| wire out; |
| assign #1 out = supply_ok ? in : 1'bx; |
| |
| endmodule |
