| ************************************************************************ |
| * auCdl Netlist: |
| * |
| * Library Name: s130iom0 |
| * Top Cell Name: ALL_Public_Cells |
| * View Name: schematic |
| * Netlisted on: Sep 30 10:12:48 2021 |
| ************************************************************************ |
| |
| *.BIPOLAR |
| *.RESI = 2000 |
| *.RESVAL |
| *.CAPVAL |
| *.DIOPERI |
| *.DIOAREA |
| *.EQUATION |
| *.SCALE METER |
| *.MEGA |
| .PARAM |
| |
| |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pudrvr_unit_2_5 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pudrvr_unit_2_5 pd pgin ps |
| *.PININFO pgin:I pd:B ps:B |
| Mmpdrv pd pgin ps ps pmos_v5 W=5 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tk_tie_r_out_esd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tk_tie_r_out_esd a b |
| *.PININFO a:B b:B |
| Rresd_r $PINS MINUS=b PLUS=a model=rpoly w=0.5 l=10.2 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pudrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pudrvr_strong pad pu_h_n<3> pu_h_n<2> tie_hi_esd vcc_io |
| + vnb |
| *.PININFO pu_h_n<3>:I pu_h_n<2>:I vcc_io:I vnb:I tie_hi_esd:O pad:B |
| XXn24<2> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn24<1> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn24<0> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn21 pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn11<2> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn11<1> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn11<0> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn23<2> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn23<1> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn23<0> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn12<2> pad net038 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn12<1> pad net038 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn12<0> pad net038 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn22 pad net45 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn13<2> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn13<1> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn13<0> pad pu_h_n<2> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn34<2> pad net076 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn34<1> pad net076 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn34<0> pad net076 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn31<2> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn31<1> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn31<0> pad pu_h_n<3> vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn32<2> pad net042 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn32<1> pad net042 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn32<0> pad net042 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn33<1> pad net075 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXn33<0> pad net075 vcc_io / s130iom0_gpio_pudrvr_unit_2_5 |
| XXI49 vcc_io tie_hi_esd / s130iom0_tk_tie_r_out_esd |
| RRM7 net076 tie_hi_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net042 pu_h_n<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net45 pu_h_n<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM0 net038 pu_h_n<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM6 net075 tie_hi_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pddrvr_unit_2_5 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pddrvr_unit_2_5 nd ngin ns |
| *.PININFO ngin:I nd:B ns:B |
| Mmndrv nd ngin ns ns nmos_v5 W=5 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_analog_pad_pddrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_analog_pad_pddrvr_strong force_lo_h force_lovol_h pad pd_h<3> |
| + pd_h<2> tie_lo_esd vcc_io vgnd_io vssd vssio_amx |
| *.PININFO force_lo_h:I force_lovol_h:I pd_h<3>:I pd_h<2>:I vcc_io:I vgnd_io:I |
| *.PININFO vssio_amx:I tie_lo_esd:O pad:B vssd:B |
| XXn11<2> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<1> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<0> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<2> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<1> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<0> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<2> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<1> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<0> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<2> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<1> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<0> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn12 pad net070 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<2> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<1> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<0> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<3> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<2> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<1> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<0> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn13 pad net078 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn31 pad net080 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXI49 vgnd_io tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| DD1 vcc_io vgnd_io dipw_dnw_v5 area=1565.510 pj=187.110 m=1 |
| DD0 vcc_io vssd ddnw_sub_v5 area=1791.380 pj=197.770 m=1 |
| RRM0 net070 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net078 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM3 net016 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM5 net057 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM6 net022 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM7 net076 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net068 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM4 net080 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_analog_pad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_analog_pad amuxbus_a amuxbus_b pad pad_core vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B pad:B pad_core:B vccd:B vcchib:B vdda:B |
| *.PININFO vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| XXpudrvr_strong pad tie_hi_esd tie_hi_esd tie_hi_esd vddio vssd / |
| + s130iom0_gpio_pudrvr_strong |
| RrI289 pad_core pad 4.7m $[rm3] $W=8.98 $L=0.9 M=1 |
| XPAD0 pad pad_bond w=60 l=70 m=1 |
| XXpddrvr_strong tie_lo_esd tie_lo_esd pad tie_lo_esd tie_lo_esd tie_lo_esd |
| + vddio vssio vssd vssio / s130iom0_analog_pad_pddrvr_strong |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amuxsplitv2_switch_levelshifter |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amuxsplitv2_switch_levelshifter fbk fbk_n hold reset |
| + switch_lv switch_lv_n vgnd vpwr_hv vpwr_lv |
| *.PININFO hold:I reset:I switch_lv:I switch_lv_n:I fbk:O fbk_n:O vgnd:B |
| *.PININFO vpwr_hv:B vpwr_lv:B |
| MmI184 fbk reset vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmI15 fbk_n hold net97 vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmI18 fbk hold net105 vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmI185 fbk_n fbk vpwr_hv vpwr_hv pmos_v5 W=0.75 L=0.5 M=1 |
| MmI20 fbk fbk_n vpwr_hv vpwr_hv pmos_v5 W=0.75 L=0.5 M=1 |
| MmI16 net109 switch_lv vgnd vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI19 net117 switch_lv_n vgnd vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI183 net97 vpwr_lv net109 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| MmI182 net105 vpwr_lv net117 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amuxsplitv2_switch_s0 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amuxsplitv2_switch_s0 hold in_lv out_h reset vccd vdda vssa |
| + vssd |
| *.PININFO hold:I in_lv:I reset:I out_h:O vccd:B vdda:B vssa:B vssd:B |
| MmI19 in_lv_i in_lv_n vccd vccd pmos_hvt W=1 L=0.25 M=1 |
| MmI20 in_lv_n in_lv vccd vccd pmos_hvt W=1 L=0.25 M=1 |
| XXI0 net17 net051 hold reset in_lv_i in_lv_n vssa vdda vccd / |
| + s130iom0_amuxsplitv2_switch_levelshifter |
| MmI21 in_lv_i in_lv_n vssd vssd nmos W=1 L=0.25 M=1 |
| MmI22 in_lv_n in_lv vssd vssd nmos W=1 L=0.25 M=1 |
| MmI16 out_h net051 vssa vssa nmos_v5 W=1 L=0.6 M=1 |
| MmI15 out_h net051 vdda vdda pmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amuxsplitv2_switch_sl |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amuxsplitv2_switch_sl hold in_lv out_h out_h_n reset vccd |
| + vdda vssa vssd vswitch |
| *.PININFO hold:I in_lv:I reset:I out_h:O out_h_n:O vccd:B vdda:B vssa:B vssd:B |
| *.PININFO vswitch:B |
| MmI16 out_h_n net39 vssa vssa nmos_v5 W=1 L=0.6 M=1 |
| MmI13 out_h net44 vssa vssa nmos_v5 W=1 L=0.6 M=1 |
| MmI19 in_lv_i in_lv_n vccd vccd pmos_hvt W=1 L=0.25 M=1 |
| MmI20 in_lv_n in_lv vccd vccd pmos_hvt W=1 L=0.25 M=1 |
| MmI21 in_lv_i in_lv_n vssd vssd nmos W=1 L=0.25 M=1 |
| MmI22 in_lv_n in_lv vssd vssd nmos W=1 L=0.25 M=1 |
| XXI0 net39 net023 hold reset in_lv_i in_lv_n vssa vdda vccd / |
| + s130iom0_amuxsplitv2_switch_levelshifter |
| XXI1 net022 net44 hold reset in_lv_i in_lv_n vssa vswitch vccd / |
| + s130iom0_amuxsplitv2_switch_levelshifter |
| MmI15 out_h_n net39 vdda vdda pmos_v5 W=3 L=0.6 M=1 |
| MmI14 out_h net44 vswitch vswitch pmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_res75only_small |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_res75only_small pad rout |
| *.PININFO pad:B rout:B |
| RrI175 $PINS MINUS=rout PLUS=pad model=rpoly w=2 l=3.15 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amuxsplitv2_switch |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amuxsplitv2_switch amuxbus_l amuxbus_r ngate_sl_h ngate_sr_h |
| + nmid_h pgate_sl_h_n pgate_sr_h_n vdda vssa vssd |
| *.PININFO ngate_sl_h:I ngate_sr_h:I nmid_h:I pgate_sl_h_n:I pgate_sr_h_n:I |
| *.PININFO amuxbus_l:B amuxbus_r:B vdda:B vssa:B vssd:B |
| DD1 vdda mid dipw_dnw_v5 area=697.4520 pj=105.640 m=1 |
| DD0 vdda vssa dipw_dnw_v5 area=526.8910 pj=145.070 m=1 |
| XXI18 vssa nmid_h_s / s130_esd_res75only_small |
| MmI1 amuxbus_l ngate_sl_h mid mid nmos_v5 W=10 L=0.5 M=30 |
| MmI2 mid ngate_sr_h amuxbus_r mid nmos_v5 W=10 L=0.5 M=30 |
| MmI4 mid nmid_h nmid_h_s vssa nmos_v5 W=5 L=0.5 M=2 |
| MmI0 mid pgate_sl_h_n amuxbus_l vdda pmos_v5 W=10 L=0.5 M=14 |
| MmI3 amuxbus_r pgate_sr_h_n mid vdda pmos_v5 W=10 L=0.5 M=14 |
| DD2 vdda vssd ddnw_sub_v5 area=1519.680 pj=162.870 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_nand2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_nand2 in0 in1 out vgnd vpwr |
| *.PININFO in0:I in1:I vgnd:I vpwr:I out:O |
| MmI3 out in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI5 out in1 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI1 out in1 net25 vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI6 net25 in0 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amuxsplitv2_delay |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amuxsplitv2_delay enable_vdda_h hld_vdda_h_n hold reset |
| + vcc_io vgnd |
| *.PININFO enable_vdda_h:I hld_vdda_h_n:I hold:O reset:O vcc_io:B vgnd:B |
| MmI36 hold reset vcc_io vcc_io pmos_v5 W=3 L=0.6 M=1 |
| MmI28 hld_vdda_h hld_vdda_h_n vcc_io vcc_io pmos_v5 W=3 L=0.6 M=1 |
| MmI13 enable_vdda_h_n enable_vdda_h vcc_io vcc_io pmos_v5 W=3 L=0.6 M=1 |
| MmI29 hld_vdda_h_n_switch hld_vdda_h vcc_io vcc_io pmos_v5 W=3 L=0.6 M=2 |
| MmI12 enable_vdda_switch enable_vdda_h_n vcc_io vcc_io pmos_v5 W=3 L=0.6 M=2 |
| MmI37 hold reset vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI30 hld_vdda_h hld_vdda_h_n vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI15 enable_vdda_h_n enable_vdda_h vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI31 hld_vdda_h_n_switch hld_vdda_h vgnd vgnd nmos_v5 W=1 L=0.6 M=2 |
| MmI14 enable_vdda_switch enable_vdda_h_n vgnd vgnd nmos_v5 W=1 L=0.6 M=2 |
| XXI33 enable_vdda_switch hld_vdda_h_n_switch reset vgnd vcc_io / |
| + s130iom0_hvsbt_nand2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_amuxsplitv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_amuxsplitv2 amuxbus_a_l amuxbus_a_r amuxbus_b_l |
| + amuxbus_b_r enable_vdda_h hld_vdda_h_n switch_aa_s0 switch_aa_sl |
| + switch_aa_sr switch_bb_s0 switch_bb_sl switch_bb_sr vccd vcchib vdda vddio |
| + vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO enable_vdda_h:I hld_vdda_h_n:I switch_aa_s0:I switch_aa_sl:I |
| *.PININFO switch_aa_sr:I switch_bb_s0:I switch_bb_sl:I switch_bb_sr:I |
| *.PININFO amuxbus_a_l:B amuxbus_a_r:B amuxbus_b_l:B amuxbus_b_r:B vccd:B |
| *.PININFO vcchib:B vdda:B vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B |
| *.PININFO vswitch:B |
| DD0 vdda vssa dipw_dnw_v5 area=756.560 pj=158.060 m=1 |
| XXI18 hold switch_aa_s0 ng_vdda_aa_s0_h reset vccd vdda vssa vssd / |
| + s130iom0_amuxsplitv2_switch_s0 |
| XXI348 hold switch_bb_s0 ng_vdda_bb_s0_h reset vccd vdda vssa vssd / |
| + s130iom0_amuxsplitv2_switch_s0 |
| XXI347 hold switch_aa_sl ng_vswitch_aa_sl_h pg_vdda_aa_sl_h_n reset vccd vdda |
| + vssa vssd vswitch / s130iom0_amuxsplitv2_switch_sl |
| XXI24 hold switch_aa_sr ng_vswitch_aa_sr_h pg_vdda_aa_sr_h_n reset vccd vdda |
| + vssa vssd vswitch / s130iom0_amuxsplitv2_switch_sl |
| XXI350 hold switch_bb_sl ng_vswitch_bb_sl_h pg_vdda_bb_sl_h_n reset vccd vdda |
| + vssa vssd vswitch / s130iom0_amuxsplitv2_switch_sl |
| XXI349 hold switch_bb_sr ng_vswitch_bb_sr_h pg_vdda_bb_sr_h_n reset vccd vdda |
| + vssa vssd vswitch / s130iom0_amuxsplitv2_switch_sl |
| DD1 vdda vssd ddnw_sub_v5 area=1042.030 pj=121.160 m=1 |
| XXI6 amuxbus_a_l amuxbus_a_r ng_vswitch_aa_sl_h ng_vswitch_aa_sr_h |
| + ng_vdda_aa_s0_h pg_vdda_aa_sl_h_n pg_vdda_aa_sr_h_n vdda vssa vssd / |
| + s130iom0_amuxsplitv2_switch |
| XXI8 amuxbus_b_l amuxbus_b_r ng_vswitch_bb_sl_h ng_vswitch_bb_sr_h |
| + ng_vdda_bb_s0_h pg_vdda_bb_sl_h_n pg_vdda_bb_sr_h_n vdda vssa vssd / |
| + s130iom0_amuxsplitv2_switch |
| XXI342 enable_vdda_h hld_vdda_h_n hold reset vdda vssa / |
| + s130iom0_amuxsplitv2_delay |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_inv_x1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_inv_x1 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI1 out in vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI2 out in vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_hvlv_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_hvlv_ls in_h out_c out_t vcchib vddio_q vssd |
| *.PININFO in_h:I vcchib:I vddio_q:I vssd:I out_c:O out_t:O |
| MmI535 out_t in_int_h_n vssd vssd nmos_v5 W=5 L=0.6 M=1 |
| MmI536 out_c in_int_h vssd vssd nmos_v5 W=5 L=0.6 M=1 |
| XXI11 in_int_h_n in_int_h vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXI10 in_h in_int_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| MmI534 out_t out_c vcchib vcchib pmos W=1 L=0.25 M=1 |
| MmI533 out_c out_t vcchib vcchib pmos W=1 L=0.25 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_inv_x4 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_inv_x4 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI1 out in vpwr vpwr pmos_v5 W=1 L=0.6 M=8 |
| MmI2 out in vgnd vgnd nmos_v5 W=0.7 L=0.6 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_buf_hys |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_buf_hys in_h out_h vcc_io vssd |
| *.PININFO in_h:I vcc_io:I vssd:I out_h:O |
| MmI9 out_h out_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI8 out_h_n in_h pmid1 vcc_io pmos_v5 W=3 L=1 M=1 |
| MmI7 pmid1 in_h vcc_io vcc_io pmos_v5 W=3 L=1 M=1 |
| MmI10 pmid1 out_h vcc_io vcc_io pmos_v5 W=0.42 L=1 M=1 |
| MmI6 out_h out_h_n vssd vssd nmos_v5 W=1 L=0.5 M=1 |
| MmI11 nmid1 out_h vssd vssd nmos_v5 W=0.42 L=1 M=1 |
| MmI4 out_h_n in_h nmid1 vssd nmos_v5 W=1 L=1 M=1 |
| MmI5 nmid1 in_h vssd vssd nmos_v5 W=1 L=1 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_res_weakv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_res_weakv2 ra rb vgnd_io |
| *.PININFO vgnd_io:I ra:B rb:B |
| RRM1 net033 net04 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| RrI104 $PINS MINUS=net04 PLUS=net033 model=rpoly w=0.8 l=6 m=1 segments=1 |
| + rType=Parallel |
| RrI134 $PINS MINUS=net033 PLUS=net034 model=rpoly w=0.8 l=6 m=1 segments=1 |
| + rType=Parallel |
| RrI116 $PINS MINUS=net034 PLUS=net64 model=rpoly w=0.8 l=12 m=1 segments=1 |
| + rType=Parallel |
| RRM2 net04 net07 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM4 net011 net014 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM5 net014 rb 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM3 net07 net011 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RrI85 $PINS MINUS=net64 PLUS=ra model=rpoly w=0.8 l=50.8 m=1 segments=1 |
| + rType=Parallel |
| RrI84 $PINS MINUS=net07 PLUS=net04 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI82 $PINS MINUS=net014 PLUS=net011 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI83 $PINS MINUS=net011 PLUS=net07 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI62 $PINS MINUS=rb PLUS=net014 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_inv_x2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_inv_x2 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI2 out in vgnd vgnd nmos_v5 W=0.7 L=0.6 M=2 |
| MmI1 out in vpwr vpwr pmos_v5 W=1 L=0.6 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_rcfilter_lpf_res_sub |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_rcfilter_lpf_res_sub in out vgnd |
| *.PININFO in:I out:O vgnd:B |
| Rrr1 $PINS B=vgnd MINUS=net05 PLUS=net_06 model=rndiff w=0.5 l=47 m=1 |
| + segments=1 rType=Parallel |
| Rrropto $PINS B=vgnd MINUS=net05 PLUS=in model=rndiff w=0.5 l=14 m=1 |
| + segments=1 rType=Parallel |
| Rrropti $PINS B=vgnd MINUS=net_06 PLUS=out model=rndiff w=0.5 l=14 m=1 |
| + segments=1 rType=Parallel |
| RRM1opt1 in net05 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_rcfilter_lpf_rcunit |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_rcfilter_lpf_rcunit in out vgnd vnb vpwr |
| *.PININFO in:I out:O vgnd:B vnb:B vpwr:B |
| XXr1b net14 out vnb / s130iom0_xres_rcfilter_lpf_res_sub |
| XXr1a in net14 vnb / s130iom0_xres_rcfilter_lpf_res_sub |
| MmI244 vpwr out vpwr vpwr pmos_v5 W=7 L=4 M=1 |
| MmI242 vgnd out vgnd vnb nmos_v5 W=7 L=4 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres2v2_rcfilter_lpf |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres2v2_rcfilter_lpf in out vcc_io vssd |
| *.PININFO in:I out:O vcc_io:B vssd:B |
| *.CONNECT net9 net09 |
| XXI196 vssd net27 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI179 net9 net15 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI174 net09 net9 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI172 in net5 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI184 vssd net18 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI185 vssd net20 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI195 vssd net13 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI178 net15 net34 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI177 net34 net38 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI176 net38 out vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI175 net7 net09 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI173 net5 net7 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_axresv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_axresv2 amuxbus_a amuxbus_b disable_pullup_h filter_in_h |
| + filter_out filter_out_h pullup_h tie_hi_esd tie_lo_esd vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO disable_pullup_h:I filter_in_h:I filter_out:O filter_out_h:O |
| *.PININFO tie_hi_esd:O tie_lo_esd:O amuxbus_a:B amuxbus_b:B pullup_h:B vccd:B |
| *.PININFO vcchib:B vdda:B vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B |
| *.PININFO vswitch:B |
| MmI32 net037 net65 vcchib vcchib pmos_hvt W=3 L=0.25 M=1 |
| MmI34 net037 net65 vssd vssd nmos W=1 L=0.25 M=2 |
| XXI326 vssio tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| XXI49 vddio tie_hi_esd / s130iom0_tk_tie_r_out_esd |
| XXhv_lv_ls out_hysbuf_h net66 net65 vcchib vddio_q vssd / s130iom0_xres_hvlv_ls |
| XXhv_drv2 out_h_n filter_out_h vssd vddio_q / s130iom0_hvsbt_inv_x4 |
| XXhv_drv1 out_hysbuf_h out_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXhyst_buf out_rcfilt_h out_hysbuf_h vddio_q vssd / s130iom0_xres_buf_hys |
| XXI330 net018 pullup_h vssd / s130iom0_com_res_weakv2 |
| MmI35 filter_out net037 vssd vssd nmos W=1 L=0.25 M=8 |
| MmI33 filter_out net037 vcchib vcchib pmos_hvt W=3 L=0.25 M=4 |
| XXI323 net080 net082 vssd vddio / s130iom0_hvsbt_inv_x2 |
| XXI324 disable_pullup_h net080 vssd vddio / s130iom0_hvsbt_inv_x2 |
| MmI321 net018 net082 vddio vddio pmos_v5 W=5 L=0.5 M=4 |
| XXrcfilt filter_in_h out_rcfilt_h vddio_q vssd / s130iom0_xres2v2_rcfilter_lpf |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_nor |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_nor in0 in1 out vgnd vpwr |
| *.PININFO in0:I in1:I vgnd:I vpwr:I out:O |
| MmI1 out in0 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI6 out in1 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI12 out in1 net16 vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI3 net16 in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_inv_x8 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_inv_x8 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI2 out in vgnd vgnd nmos_v5 W=0.7 L=0.6 M=8 |
| MmI1 out in vpwr vpwr pmos_v5 W=1 L=0.6 M=16 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_ctl_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_ctl_ls hld_h_n in out_h out_h_n rst_h set_h vcc_io vgnd |
| + vpwr |
| *.PININFO hld_h_n:I in:I rst_h:I set_h:I vcc_io:I vgnd:I vpwr:I out_h:O |
| *.PININFO out_h_n:O |
| MmI2 fbk fbk_n vcc_io vcc_io pmos_v5 W=0.75 L=0.5 M=1 |
| MmI1 fbk_n fbk vcc_io vcc_io pmos_v5 W=0.75 L=0.5 M=1 |
| MmI14 out_h_n fbk vcc_io vcc_io pmos_v5 W=3 L=0.6 M=1 |
| MmI11 out_h fbk_n vcc_io vcc_io pmos_v5 W=3 L=0.6 M=1 |
| MmI13 out_h_n fbk vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI12 out_h fbk_n vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI32 in_i in_i_n vgnd vgnd nmos W=1 L=0.25 M=1 |
| MmI27 in_i_n in vgnd vgnd nmos W=1 L=0.25 M=1 |
| MmI34 in_i in_i_n vpwr vpwr pmos_hvt W=1 L=0.25 M=1 |
| MmI29 in_i_n in vpwr vpwr pmos_hvt W=1 L=0.25 M=1 |
| MmI7 net94 in_i_n vgnd vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI8 net98 in_i vgnd vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI58 net130 vpwr net94 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| MmI59 net122 vpwr net98 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| MmI4 fbk_n fbk vgnd vgnd nmos_v5 W=0.75 L=1 M=1 |
| MmI3 fbk fbk_n vgnd vgnd nmos_v5 W=0.75 L=1 M=1 |
| Mmmnset fbk_n set_h vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| Mmmnrst fbk rst_h vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmI5 fbk hld_h_n net130 vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmI6 fbk_n hld_h_n net122 vgnd nmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ctl_hld |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ctl_hld enable_h hld_h_n hld_i_h hld_i_h_n hld_i_ovr_h |
| + hld_ovr od_i_h vcc_io vgnd vpwr |
| *.PININFO enable_h:I hld_h_n:I hld_ovr:I vcc_io:I vgnd:I vpwr:I hld_i_h:O |
| *.PININFO hld_i_h_n:O hld_i_ovr_h:O od_i_h:O |
| Rrshort_hld_i_h enable_vdda_h_n hld_i_h 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| XXI31 od_i_h_n od_i_h vgnd vcc_io / s130iom0_hvsbt_inv_x4 |
| XXhld_i_h_inv4 net65 enable_vdda_h_n vgnd vcc_io / s130iom0_hvsbt_inv_x4 |
| XXI32 od_h od_i_h_n vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXod_h_inv enable_h od_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXhld_i_h_inv1 net64 net65 vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI30 od_i_h hld_i_ovr_h_n hld_i_ovr_h vgnd vcc_io / s130iom0_hvsbt_nor |
| XXI26 net65 hld_ovr_h hld_i_ovr_h_n vgnd vcc_io / s130iom0_hvsbt_nor |
| XXhld_i_h_inv8<1> enable_vdda_h_n hld_i_h_n_net<1> vgnd vcc_io / |
| + s130iom0_hvsbt_inv_x8 |
| XXhld_i_h_inv8<0> enable_vdda_h_n hld_i_h_n_net<0> vgnd vcc_io / |
| + s130iom0_hvsbt_inv_x8 |
| XXhld_nand enable_h hld_h_n net64 vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXhld_ovr_ls net65 hld_ovr hld_ovr_h net37 od_h vgnd vcc_io vgnd vpwr / |
| + s130iom0_com_ctl_ls |
| Rrshort<1> hld_i_h_n_net<1> hld_i_h_n 13.6m $[rm1] $W=0.23 $L=0.025 M=1 |
| Rrshort<0> hld_i_h_n_net<0> hld_i_h_n 13.6m $[rm1] $W=0.23 $L=0.025 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ctl_lsbank |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ctl_lsbank dm<2> dm<1> dm<0> dm_h<2> dm_h<1> dm_h<0> |
| + dm_h_n<2> dm_h_n<1> dm_h_n<0> hld_i_h_n ib_mode_sel ib_mode_sel_h |
| + ib_mode_sel_h_n inp_dis inp_dis_h inp_dis_h_n od_i_h startup_rst_h |
| + startup_st_h vcc_io vgnd vpwr vtrip_sel vtrip_sel_h vtrip_sel_h_n |
| *.PININFO dm<2>:I dm<1>:I dm<0>:I hld_i_h_n:I ib_mode_sel:I inp_dis:I od_i_h:I |
| *.PININFO startup_rst_h:I startup_st_h:I vcc_io:I vgnd:I vpwr:I vtrip_sel:I |
| *.PININFO dm_h<2>:O dm_h<1>:O dm_h<0>:O dm_h_n<2>:O dm_h_n<1>:O dm_h_n<0>:O |
| *.PININFO ib_mode_sel_h:O ib_mode_sel_h_n:O inp_dis_h:O inp_dis_h_n:O |
| *.PININFO vtrip_sel_h:O vtrip_sel_h_n:O |
| XXtrip_sel_ls hld_i_h_n vtrip_sel vtrip_sel_h vtrip_sel_h_n trip_sel_rst_h |
| + trip_sel_st_h vcc_io vgnd vpwr / s130iom0_com_ctl_ls |
| XXinp_dis_ls hld_i_h_n inp_dis inp_dis_h inp_dis_h_n ie_n_rst_h ie_n_st_h |
| + vcc_io vgnd vpwr / s130iom0_com_ctl_ls |
| XXI595 hld_i_h_n ib_mode_sel ib_mode_sel_h ib_mode_sel_h_n ib_mode_sel_rst_h |
| + ib_mode_sel_st_h vcc_io vgnd vpwr / s130iom0_com_ctl_ls |
| XXdm_ls<2> hld_i_h_n dm<2> dm_h<2> dm_h_n<2> dm_rst_h<2> dm_st_h<2> vcc_io |
| + vgnd vpwr / s130iom0_com_ctl_ls |
| XXdm_ls<1> hld_i_h_n dm<1> dm_h<1> dm_h_n<1> dm_rst_h<1> dm_st_h<1> vcc_io |
| + vgnd vpwr / s130iom0_com_ctl_ls |
| XXdm_ls<0> hld_i_h_n dm<0> dm_h<0> dm_h_n<0> dm_rst_h<0> dm_st_h<0> vcc_io |
| + vgnd vpwr / s130iom0_com_ctl_ls |
| RRM7 od_i_h trip_sel_rst_h 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM10 startup_st_h ie_n_rst_h 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM1 od_i_h dm_rst_h<1> 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM2 startup_rst_h dm_rst_h<0> 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM0 od_i_h dm_rst_h<2> 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM6 vgnd trip_sel_st_h 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM3 vgnd dm_st_h<1> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM4 startup_st_h dm_st_h<0> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM5 vgnd dm_st_h<2> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM11 startup_rst_h ie_n_st_h 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM8 vgnd ib_mode_sel_st_h 4.8m $[rm2] $W=0.26 $L=0.01 M=1 |
| RRM9 od_i_h ib_mode_sel_rst_h 4.8m $[rm2] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ctl |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ctl dm<2> dm<1> dm<0> dm_h<2> dm_h<1> dm_h<0> |
| + dm_h_n<2> dm_h_n<1> dm_h_n<0> enable_h enable_inp_h hld_h_n hld_i_h |
| + hld_i_h_n hld_i_ovr_h hld_ovr ib_mode_sel ib_mode_sel_h ib_mode_sel_h_n |
| + inp_dis inp_dis_h_n od_i_h vcc_io vgnd vpwr vtrip_sel vtrip_sel_h |
| + vtrip_sel_h_n |
| *.PININFO dm<2>:I dm<1>:I dm<0>:I enable_h:I enable_inp_h:I hld_h_n:I |
| *.PININFO hld_ovr:I ib_mode_sel:I inp_dis:I vcc_io:I vgnd:I vpwr:I vtrip_sel:I |
| *.PININFO dm_h<2>:O dm_h<1>:O dm_h<0>:O dm_h_n<2>:O dm_h_n<1>:O dm_h_n<0>:O |
| *.PININFO hld_i_h:O hld_i_h_n:O hld_i_ovr_h:O ib_mode_sel_h:O |
| *.PININFO ib_mode_sel_h_n:O inp_dis_h_n:O od_i_h:O vtrip_sel_h:O |
| *.PININFO vtrip_sel_h_n:O |
| XXI56 od_i_h enable_inp_h net92 vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI57 net92 inp_startup_en_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI75 enable_inp_h enable_h startup_rst_h vgnd vcc_io / s130iom0_hvsbt_nor |
| XXhld_dis_blk enable_h hld_h_n hld_i_h hld_i_h_n hld_i_ovr_h hld_ovr od_i_h |
| + vcc_io vgnd vpwr / s130iom0_gpiov2_ctl_hld |
| XXls_bank dm<2> dm<1> dm<0> dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> |
| + dm_h_n<0> hld_i_h_n ib_mode_sel ib_mode_sel_h ib_mode_sel_h_n inp_dis net80 |
| + inp_dis_h_n od_i_h startup_rst_h inp_startup_en_h vcc_io vgnd vpwr vtrip_sel |
| + vtrip_sel_h vtrip_sel_h_n / s130iom0_gpiov2_ctl_lsbank |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_switch |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_switch amuxbus_hv ng_amx_vpmp_h ng_pad_vpmp_h |
| + nmid_vccd pad_hv_n0 pad_hv_n1 pad_hv_n2 pad_hv_n3 pad_hv_p0 pad_hv_p1 |
| + pd_h_vdda pd_h_vddio pg_amx_vdda_h_n pg_pad_vddioq_h_n vdda vddio vssa vssd |
| *.PININFO ng_amx_vpmp_h:I ng_pad_vpmp_h:I nmid_vccd:I pd_h_vdda:I pd_h_vddio:I |
| *.PININFO pg_amx_vdda_h_n:I pg_pad_vddioq_h_n:I vdda:I vddio:I vssa:I vssd:I |
| *.PININFO amuxbus_hv:B pad_hv_n0:B pad_hv_n1:B pad_hv_n2:B pad_hv_n3:B |
| *.PININFO pad_hv_p0:B pad_hv_p1:B |
| XXI56 vssa net_94 / s130_esd_res75only_small |
| XXI12 vssa net_130 / s130_esd_res75only_small |
| MmI28 mid ng_amx_vpmp_h amuxbus_hv mid nmos_v5 W=7 L=0.5 M=7 |
| MmI47 mid1 ng_amx_vpmp_h amuxbus_hv mid1 nmos_v5 W=7 L=0.5 M=7 |
| MmI57 mid1 nmid_vccd net_94 vssa nmos_v5 W=3 L=0.5 M=1 |
| MmI1 mid nmid_vccd net_130 vssa nmos_v5 W=3 L=0.5 M=1 |
| MmI77<1> mid pd_h_vddio vssa vssa nmos_v5 W=0.42 L=0.5 M=1 |
| MmI77<0> mid1 pd_h_vddio vssa vssa nmos_v5 W=0.42 L=0.5 M=1 |
| MmI78<1> mid pd_h_vdda vssa vssa nmos_v5 W=0.42 L=0.5 M=1 |
| MmI78<0> mid1 pd_h_vdda vssa vssa nmos_v5 W=0.42 L=0.5 M=1 |
| DD1 vdda mid1 dipw_dnw_v5 area=144.7470 pj=49.610 m=1 |
| DD0 vdda mid dipw_dnw_v5 area=141.4190 pj=48.370 m=1 |
| MmI26 mid pg_amx_vdda_h_n amuxbus_hv vdda pmos_v5 W=7 L=0.5 M=5 |
| MmI35 mid ng_pad_vpmp_h pad_hv_n1 mid nmos_v5 W=7 L=0.5 M=4 |
| MmI46 pad_hv_n3 ng_pad_vpmp_h mid1 mid1 nmos_v5 W=7 L=0.5 M=4 |
| MmI45 mid1 ng_pad_vpmp_h pad_hv_n2 mid1 nmos_v5 W=7 L=0.5 M=4 |
| MmI24 pad_hv_n0 ng_pad_vpmp_h mid mid nmos_v5 W=7 L=0.5 M=3 |
| MmI22 mid pg_pad_vddioq_h_n pad_hv_p1 vddio pmos_v5 W=7 L=0.5 M=3 |
| MmI36 mid pg_pad_vddioq_h_n pad_hv_p0 vddio pmos_v5 W=7 L=0.5 M=3 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_inv_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_inv_1 A Y vgnd vnb vpb vpwr |
| *.PININFO A:I vgnd:I vnb:I vpb:I vpwr:I Y:O |
| MmMIN1 Y A vgnd vnb nmos W=0.74 L=0.15 M=1 |
| MmMIP1 Y A vpwr vpb pmos_hvt W=1.12 L=0.15 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_nor2_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_nor2_1 A B Y vgnd vnb vpb vpwr |
| *.PININFO A:I B:I vgnd:I vnb:I vpb:I vpwr:I Y:O |
| MmMP1 Y B sndPA vpb pmos_hvt W=1.12 L=0.15 M=1 |
| MmMP0 sndPA A vpwr vpb pmos_hvt W=1.12 L=0.15 M=1 |
| MmMN0 Y A vgnd vnb nmos W=0.74 L=0.15 M=1 |
| MmMN1 Y B vgnd vnb nmos W=0.74 L=0.15 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_nand2_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_nand2_1 A B Y vgnd vnb vpb vpwr |
| *.PININFO A:I B:I vgnd:I vnb:I vpb:I vpwr:I Y:O |
| MmMP0 Y A vpwr vpb pmos_hvt W=1.12 L=0.15 M=1 |
| MmMP1 Y B vpwr vpb pmos_hvt W=1.12 L=0.15 M=1 |
| MmMN0 Y A sndA vnb nmos W=0.74 L=0.15 M=1 |
| MmMN1 sndA B vgnd vnb nmos W=0.74 L=0.15 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xor2_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xor2_1 A B X vgnd vpwr |
| *.PININFO A:I B:I vgnd:I vpwr:I X:O |
| MmMNaoi10 sndNA A vgnd vgnd nmos W=0.8400000000000001 L=0.15 M=1 |
| MmMNaoi11 X B sndNA vgnd nmos W=0.8400000000000001 L=0.15 M=1 |
| MmMNnor0 inor A vgnd vgnd nmos W=0.8400000000000001 L=0.15 M=1 |
| MmMNnor1 inor B vgnd vgnd nmos W=0.8400000000000001 L=0.15 M=1 |
| MmMNaoi20 X inor vgnd vgnd nmos W=0.8400000000000001 L=0.15 M=1 |
| MmMPnor1 inor B sndPA vpwr pmos_hvt W=1.26 L=0.15 M=1 |
| MmMPnor0 sndPA A vpwr vpwr pmos_hvt W=1.26 L=0.15 M=1 |
| MmMPaoi10 pmid A vpwr vpwr pmos_hvt W=1.26 L=0.15 M=1 |
| MmMPaoi11 pmid B vpwr vpwr pmos_hvt W=1.26 L=0.15 M=1 |
| MmMPaoi20 X inor pmid vpwr pmos_hvt W=1.26 L=0.15 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_nand5 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_nand5 in0 in1 in2 in3 in4 out vgnd vpwr |
| *.PININFO in0:I in1:I in2:I in3:I in4:I vgnd:I vpwr:I out:O |
| MmI3 out in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI21 out_n out vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI20 out out_n vpwr vpwr pmos_v5 W=0.42 L=0.5 M=1 |
| MmI22 out_n out vgnd vgnd nmos_v5 W=0.42 L=0.5 M=1 |
| MmI23 vgnd out_n vgnd vgnd nmos_v5 W=0.42 L=0.5 M=1 |
| MmI1 out in1 net51 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI15 net55 in3 net63 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI14 net51 in2 net55 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI6 net59 in0 vgnd vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI18 net63 in4 net59 vgnd nmos_v5 W=5 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_nand4 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_nand4 in0 in1 in2 in3 out vgnd vpwr |
| *.PININFO in0:I in1:I in2:I in3:I vgnd:I vpwr:I out:O |
| MmI3 out in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI19 out_n out vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI20 out out_n vpwr vpwr pmos_v5 W=0.42 L=0.5 M=1 |
| MmI18 out_n out vgnd vgnd nmos_v5 W=0.42 L=0.5 M=1 |
| MmI21 vgnd out_n vgnd vgnd nmos_v5 W=0.42 L=0.5 M=1 |
| MmI1 out in1 net50 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI14 net50 in2 net54 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI6 net58 in0 vgnd vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI15 net54 in3 net58 vgnd nmos_v5 W=5 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_decoder |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_decoder amuxbusa_on amuxbusa_on_n amuxbusb_on |
| + amuxbusb_on_n analog_en analog_pol analog_sel nga_pad_vswitch_h |
| + nga_pad_vswitch_h_n ngb_pad_vswitch_h ngb_pad_vswitch_h_n nmida_on_n |
| + nmida_vccd_n nmidb_on_n nmidb_vccd_n out pd_on pd_on_n pd_vswitch_h_n |
| + pga_amx_vdda_h_n pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n |
| + pu_on pu_on_n pu_vddioq_h_n vccd vssd |
| *.PININFO analog_en:I analog_pol:I analog_sel:I nga_pad_vswitch_h:I |
| *.PININFO nga_pad_vswitch_h_n:I ngb_pad_vswitch_h:I ngb_pad_vswitch_h_n:I |
| *.PININFO nmida_vccd_n:I nmidb_vccd_n:I out:I pd_vswitch_h_n:I |
| *.PININFO pga_amx_vdda_h_n:I pga_pad_vddioq_h_n:I pgb_amx_vdda_h_n:I |
| *.PININFO pgb_pad_vddioq_h_n:I pu_vddioq_h_n:I vccd:I vssd:I amuxbusa_on:O |
| *.PININFO amuxbusa_on_n:O amuxbusb_on:O amuxbusb_on_n:O nmida_on_n:O |
| *.PININFO nmidb_on_n:O pd_on:O pd_on_n:O pu_on:O pu_on_n:O |
| XXI93 pu_on pu_on_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI95 pd_on pd_on_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI43 out out_i_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI35 analog_pol ana_pol_i_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI58 analog_en ana_en_i_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI39 analog_sel ana_sel_i_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI74 amuxbusb_on_n amuxbusb_on vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI73 amuxbusa_on_n amuxbusa_on vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI75 int_fbk_puon_n pu_on vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI76 int_fbk_pdon_n pd_on vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI41 ana_pol_i_n ana_pol_i vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI44 out_i_n out_i vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI91 int_amuxb_on int_amux_b_on_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI89 int_amuxa_on int_amux_a_on_n vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI40 ana_sel_i_n ana_sel_i vssd vssd vccd vccd / s130iom0_inv_1 |
| XXI115 ana_en_i_n int_pu_on_n int_pu_on vssd vssd vccd vccd / s130iom0_nor2_1 |
| XXI116 ana_en_i_n int_pd_on_n int_pd_on vssd vssd vccd vccd / s130iom0_nor2_1 |
| XXI113 ana_en_i_n net0199 int_amuxa_on vssd vssd vccd vccd / s130iom0_nor2_1 |
| XXI114 ana_en_i_n net137 int_amuxb_on vssd vssd vccd vccd / s130iom0_nor2_1 |
| XXI112 ana_pol_i_n out_i_n int_pd_on_n vssd vssd vccd vccd / s130iom0_nand2_1 |
| XXI111 ana_pol_i out_i int_pu_on_n vssd vssd vccd vccd / s130iom0_nand2_1 |
| XXI109 ana_sel_i_n pol_xor_out net0199 vssd vssd vccd vccd / s130iom0_nand2_1 |
| XXI110 pol_xor_out ana_sel_i net137 vssd vssd vccd vccd / s130iom0_nand2_1 |
| XXI45 ana_pol_i out_i pol_xor_out vssd vccd / s130iom0_xor2_1 |
| XXI79 int_pu_on pga_pad_vddioq_h_n pgb_pad_vddioq_h_n nga_pad_vswitch_h_n |
| + ngb_pad_vswitch_h_n int_fbk_puon_n vssd vccd / s130iom0_gpiov2_amux_nand5 |
| XXI80 int_pd_on pga_pad_vddioq_h_n pgb_pad_vddioq_h_n nga_pad_vswitch_h_n |
| + ngb_pad_vswitch_h_n int_fbk_pdon_n vssd vccd / s130iom0_gpiov2_amux_nand5 |
| XXI78 int_amuxb_on pu_vddioq_h_n pd_vswitch_h_n nmidb_vccd_n amuxbusb_on_n |
| + vssd vccd / s130iom0_gpiov2_amux_nand4 |
| XXI77 int_amuxa_on pu_vddioq_h_n pd_vswitch_h_n nmida_vccd_n amuxbusa_on_n |
| + vssd vccd / s130iom0_gpiov2_amux_nand4 |
| XXI105 pgb_pad_vddioq_h_n pgb_amx_vdda_h_n net212 vssd vccd / |
| + s130iom0_hvsbt_nand2 |
| XXI121 int_amux_b_on_n net0283 nmidb_on_n vssd vccd / s130iom0_hvsbt_nand2 |
| XXI101 pga_pad_vddioq_h_n pga_amx_vdda_h_n net0247 vssd vccd / |
| + s130iom0_hvsbt_nand2 |
| XXI120 int_amux_a_on_n net0291 nmida_on_n vssd vccd / s130iom0_hvsbt_nand2 |
| XXI106 ngb_pad_vswitch_h net212 net0283 vssd vccd / s130iom0_hvsbt_nor |
| XXI102 nga_pad_vswitch_h net0247 net0291 vssd vccd / s130iom0_hvsbt_nor |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_drvr_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_drvr_ls in in_b out_h out_h_n rst_h rst_h_n vgnd |
| + vpwr_hv vpwr_lv |
| *.PININFO in:I in_b:I rst_h:I rst_h_n:I vgnd:I vpwr_hv:I vpwr_lv:I out_h:O |
| *.PININFO out_h_n:O |
| MmI17 out_h rst_h vgnd vgnd nmos_v5 W=1.5 L=0.5 M=2 |
| MmI25 out_h rst_h_n net030 vgnd nmos_v5 W=1.5 L=0.5 M=2 |
| MmI24 out_h_n rst_h_n net012 vgnd nmos_v5 W=1.5 L=0.5 M=2 |
| MmI11 out_h_n out_h vpwr_hv vpwr_hv pmos_v5 W=0.7 L=0.6 M=1 |
| MmI9 out_h out_h_n vpwr_hv vpwr_hv pmos_v5 W=0.7 L=0.6 M=1 |
| MmI12 net054 in_b vgnd vgnd nmos_lvt W=1 L=0.15 M=2 |
| MmI6 net052 in vgnd vgnd nmos_lvt W=1 L=0.15 M=2 |
| MmI21 net012 vpwr_lv net052 vgnd nmos_nat_v5 W=1 L=0.9 M=2 |
| MmI20 net030 vpwr_lv net054 vgnd nmos_nat_v5 W=1 L=0.9 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amx_inv4 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amx_inv4 A Y vda vssa |
| *.PININFO A:I vda:I vssa:I Y:O |
| MmI75 Y A vssa vssa nmos_v5 W=0.42 L=0.6 M=2 |
| MmI74 Y A vda vda pmos_v5 W=1 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amx_pdcsd_inv |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amx_pdcsd_inv A Y vda vssa |
| *.PININFO A:I vda:I vssa:I Y:O |
| MmI414 Y A vssa vssa nmos_v5 W=1.5 L=0.5 M=1 |
| MmI519 Y vssa vssa vssa nmos_v5 W=1.5 L=0.5 M=1 |
| MmI517 Y A vda vda pmos_v5 W=0.75 L=2 M=1 |
| MmI429 Y A vda vda pmos_v5 W=0.75 L=2 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_amx_inv1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_amx_inv1 A Y vda vssa |
| *.PININFO A:I vda:I vssa:I Y:O |
| MmI92 Y A vssa vssa nmos_v5 W=0.75 L=0.5 M=1 |
| MmI54 Y A vda vda pmos_v5 W=1.5 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amx_pucsd_inv |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amx_pucsd_inv A Y vda vssa |
| *.PININFO A:I vda:I vssa:I Y:O |
| MmI75 Y A vssa vssa nmos_v5 W=0.42 L=0.6 M=7 |
| MmI74 Y A vda vda pmos_v5 W=1 L=0.6 M=7 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_drvr_lshv2hv |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_drvr_lshv2hv in in_b out_h_n rst_h rst_h_n vgnd |
| + vpwr_hv |
| *.PININFO in:I in_b:I rst_h:I rst_h_n:I vgnd:I vpwr_hv:I out_h_n:O |
| MmI2 fbk fbk_n vpwr_hv vpwr_hv pmos_v5 W=0.42 L=1 M=1 |
| MmI1 fbk_n fbk vpwr_hv vpwr_hv pmos_v5 W=0.42 L=1 M=1 |
| MmI14 out_h_n fbk vpwr_hv vpwr_hv pmos_v5 W=1 L=0.5 M=2 |
| Mmmnrst fbk rst_h vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI13 out_h_n fbk vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI8 fbk_n in net52 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI7 fbk in_b net52 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI64 net52 rst_h_n vgnd vgnd nmos_v5 W=3 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_drvr |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_drvr amux_en_vdda_h amux_en_vdda_h_n |
| + amux_en_vddio_h amux_en_vddio_h_n amux_en_vswitch_h amux_en_vswitch_h_n |
| + amuxbusa_on amuxbusa_on_n amuxbusb_on amuxbusb_on_n nga_amx_vswitch_h |
| + nga_pad_vswitch_h nga_pad_vswitch_h_n ngb_amx_vswitch_h ngb_pad_vswitch_h |
| + ngb_pad_vswitch_h_n nmida_on_n nmida_vccd nmida_vccd_n nmidb_on_n nmidb_vccd |
| + nmidb_vccd_n pd_csd_vswitch_h pd_csd_vswitch_h_n pd_on pd_on_n |
| + pga_amx_vdda_h_n pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n |
| + pu_csd_vddioq_h_n pu_on pu_on_n vccd vdda vddio_q vssa vssd vswitch |
| *.PININFO amux_en_vdda_h:I amux_en_vdda_h_n:I amux_en_vddio_h:I |
| *.PININFO amux_en_vddio_h_n:I amux_en_vswitch_h:I amux_en_vswitch_h_n:I |
| *.PININFO amuxbusa_on:I amuxbusa_on_n:I amuxbusb_on:I amuxbusb_on_n:I |
| *.PININFO nmida_on_n:I nmidb_on_n:I pd_on:I pd_on_n:I pu_on:I pu_on_n:I vccd:I |
| *.PININFO vdda:I vddio_q:I vssa:I vssd:I vswitch:I nga_amx_vswitch_h:O |
| *.PININFO nga_pad_vswitch_h:O nga_pad_vswitch_h_n:O ngb_amx_vswitch_h:O |
| *.PININFO ngb_pad_vswitch_h:O ngb_pad_vswitch_h_n:O nmida_vccd:O |
| *.PININFO nmida_vccd_n:O nmidb_vccd:O nmidb_vccd_n:O pd_csd_vswitch_h:O |
| *.PININFO pd_csd_vswitch_h_n:O pga_amx_vdda_h_n:O pga_pad_vddioq_h_n:O |
| *.PININFO pgb_amx_vdda_h_n:O pgb_pad_vddioq_h_n:O pu_csd_vddioq_h_n:O |
| XXpu_csd_ls pu_on pu_on_n net274 net275 amux_en_vddio_h_n amux_en_vddio_h vssd |
| + vddio_q vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXpd_csd_ls pd_on pd_on_n net248 net254 amux_en_vswitch_h_n amux_en_vswitch_h |
| + vssa vswitch vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXnga_ls amuxbusa_on amuxbusa_on_n net257 net256 amux_en_vswitch_h_n |
| + amux_en_vswitch_h vssa vswitch vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXngb_ls amuxbusb_on amuxbusb_on_n net230 net236 amux_en_vswitch_h_n |
| + amux_en_vswitch_h vssa vswitch vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXpga_pad_ls amuxbusa_on amuxbusa_on_n net265 net272 amux_en_vddio_h_n |
| + amux_en_vddio_h vssd vddio_q vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXpgb_pad_ls amuxbusb_on amuxbusb_on_n net239 net245 amux_en_vddio_h_n |
| + amux_en_vddio_h vssd vddio_q vccd / s130iom0_gpiov2_amux_drvr_ls |
| XXI42 net265 pga_pad_vddioq_h_n vddio_q vssd / s130iom0_gpiov2_amx_inv4 |
| XXI62 net239 pgb_pad_vddioq_h_n vddio_q vssd / s130iom0_gpiov2_amx_inv4 |
| XXI64 net236 ngb_pad_vswitch_h vswitch vssa / s130iom0_gpiov2_amx_inv4 |
| XXI47 net256 nga_pad_vswitch_h vswitch vssa / s130iom0_gpiov2_amx_inv4 |
| XXI45 net256 nga_amx_vswitch_h vswitch vssa / s130iom0_gpiov2_amx_inv4 |
| XXI63 net236 ngb_amx_vswitch_h vswitch vssa / s130iom0_gpiov2_amx_inv4 |
| MmI77 ngb_pad_vswitch_h amux_en_vddio_h_n vssa vssa nmos_v5 W=1 L=0.5 M=1 |
| MmI78 nga_pad_vswitch_h amux_en_vddio_h_n vssa vssa nmos_v5 W=1 L=0.5 M=1 |
| MmI104 pd_csd_vswitch_h amux_en_vddio_h_n vssa vssa nmos_v5 W=1 L=0.5 M=1 |
| MmI75 nga_amx_vswitch_h amux_en_vdda_h_n vssa vssa nmos_v5 W=1 L=0.5 M=1 |
| MmI76 ngb_amx_vswitch_h amux_en_vdda_h_n vssa vssa nmos_v5 W=1 L=0.5 M=1 |
| XXI105 nmidb_vccd nmidb_vccd_n vssd vccd / s130iom0_hvsbt_inv_x1 |
| XXI93 nmida_vccd nmida_vccd_n vssd vccd / s130iom0_hvsbt_inv_x1 |
| XXpdcsd_inv net254 pd_csd_vswitch_h vswitch vssa / |
| + s130iom0_gpiov2_amx_pdcsd_inv |
| XXI53 nmidb_on_n nmidb_vccd vssd vccd / s130iom0_hvsbt_inv_x2 |
| XXI89 nmida_on_n nmida_vccd vssd vccd / s130iom0_hvsbt_inv_x2 |
| XXI87 nga_pad_vswitch_h nga_pad_vswitch_h_n vswitch vssa / s130iom0_amx_inv1 |
| XXI85 ngb_pad_vswitch_h ngb_pad_vswitch_h_n vswitch vssa / s130iom0_amx_inv1 |
| XXI90 pd_csd_vswitch_h pd_csd_vswitch_h_n vswitch vssa / s130iom0_amx_inv1 |
| XXI38 net274 pu_csd_vddioq_h_n vddio_q vssd / s130iom0_gpiov2_amx_pucsd_inv |
| XXI103 net239 net245 pgb_amx_vdda_h_n amux_en_vdda_h_n amux_en_vdda_h vssa |
| + vdda / s130iom0_gpiov2_amux_drvr_lshv2hv |
| XXpga_amx_ls net265 net272 pga_amx_vdda_h_n amux_en_vdda_h_n amux_en_vdda_h |
| + vssa vdda / s130iom0_gpiov2_amux_drvr_lshv2hv |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ctl_inv_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ctl_inv_1 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI27 out in vgnd vgnd nmos W=0.74 L=0.15 M=1 |
| MmI29 out in vpwr vpwr pmos_hvt W=1 L=0.25 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ctl_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ctl_ls in in_b out_h out_h_n rst_h rst_h_n vgnd |
| + vpwr_hv vpwr_lv |
| *.PININFO in:I in_b:I rst_h:I rst_h_n:I vgnd:I vpwr_hv:I vpwr_lv:I out_h:O |
| *.PININFO out_h_n:O |
| Mmmnrst fbk rst_h vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI13 out_h fbk_n vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI12 out_h_n fbk vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI14 out_h fbk_n vpwr_hv vpwr_hv pmos_v5 W=1.5 L=0.5 M=1 |
| MmI11 out_h_n fbk vpwr_hv vpwr_hv pmos_v5 W=1.5 L=0.5 M=1 |
| MmI2 fbk_n fbk vpwr_hv vpwr_hv pmos_v5 W=0.75 L=0.5 M=1 |
| MmI1 fbk fbk_n vpwr_hv vpwr_hv pmos_v5 W=0.75 L=0.5 M=1 |
| MmI5 net61 rst_h_n vgnd vgnd nmos_v5 W=1 L=0.5 M=4 |
| MmI8 net66 in net61 vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI7 net62 in_b net61 vgnd nmos_lvt W=1 L=0.15 M=4 |
| MmI59 fbk_n vpwr_lv net66 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| MmI58 fbk vpwr_lv net62 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ctl_lshv2hv |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ctl_lshv2hv in in_b out_h out_h_n rst_h rst_h_n |
| + vgnd vpwr_hv |
| *.PININFO in:I in_b:I rst_h:I rst_h_n:I vgnd:I vpwr_hv:I out_h:O out_h_n:O |
| Mmmnrst fbk rst_h vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI12 out_h fbk_n vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI13 out_h_n fbk vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI11 out_h fbk_n vpwr_hv vpwr_hv pmos_v5 W=1.5 L=0.5 M=1 |
| MmI14 out_h_n fbk vpwr_hv vpwr_hv pmos_v5 W=1.5 L=0.5 M=1 |
| MmI8 fbk_n in net06 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI7 fbk in_b net06 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI2 fbk fbk_n vpwr_hv vpwr_hv pmos_v5 W=0.42 L=1 M=1 |
| MmI1 fbk_n fbk vpwr_hv vpwr_hv pmos_v5 W=0.42 L=1 M=1 |
| MmI64 net06 rst_h_n vgnd vgnd nmos_v5 W=3 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ls_inv_x1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ls_inv_x1 in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI2 out in vgnd vgnd nmos_v5 W=1 L=0.5 M=1 |
| MmI1 out in vpwr vpwr pmos_v5 W=1.5 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ls amux_en_vdda_h amux_en_vdda_h_n |
| + amux_en_vddio_h amux_en_vddio_h_n amux_en_vswitch_h amux_en_vswitch_h_n |
| + analog_en enable_vdda_h enable_vdda_h_n enable_vswitch_h hld_i_h hld_i_h_n |
| + vccd vdda vddio_q vssa vssd vswitch |
| *.PININFO analog_en:I enable_vdda_h:I enable_vswitch_h:I hld_i_h:I hld_i_h_n:I |
| *.PININFO vccd:I vdda:I vddio_q:I vssa:I vssd:I vswitch:I amux_en_vdda_h:O |
| *.PININFO amux_en_vdda_h_n:O amux_en_vddio_h:O amux_en_vddio_h_n:O |
| *.PININFO amux_en_vswitch_h:O amux_en_vswitch_h_n:O enable_vdda_h_n:O |
| XXI15 analog_en ana_en_i_n vssd vccd / s130iom0_gpiov2_amux_ctl_inv_1 |
| XXI16 ana_en_i_n ana_en_i vssd vccd / s130iom0_gpiov2_amux_ctl_inv_1 |
| XXpd_vddio_ls ana_en_i ana_en_i_n amux_en_vddio_h amux_en_vddio_h_n hld_i_h |
| + hld_i_h_n vssd vddio_q vccd / s130iom0_gpiov2_amux_ctl_ls |
| XXpd_vswitch_ls amux_en_vddio_h amux_en_vddio_h_n amux_en_vswitch_h |
| + amux_en_vswitch_h_n net74 enable_vswitch_h vssa vswitch / |
| + s130iom0_gpiov2_amux_ctl_lshv2hv |
| XXpd_vdda_ls amux_en_vddio_h amux_en_vddio_h_n amux_en_vdda_h amux_en_vdda_h_n |
| + enable_vdda_h_n enable_vdda_h vssa vdda / s130iom0_gpiov2_amux_ctl_lshv2hv |
| XXI32 enable_vdda_h enable_vdda_h_n vssa vdda / s130iom0_gpiov2_amux_ls_inv_x1 |
| XXI18 enable_vswitch_h net74 vssa vswitch / s130iom0_hvsbt_inv_x1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux_ctl_logic |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux_ctl_logic analog_en analog_pol analog_sel |
| + enable_vdda_h enable_vdda_h_n enable_vswitch_h hld_i_h hld_i_h_n |
| + nga_amx_vswitch_h nga_pad_vswitch_h ngb_amx_vswitch_h ngb_pad_vswitch_h |
| + nmida_vccd nmidb_vccd out pd_csd_vswitch_h pga_amx_vdda_h_n |
| + pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n pu_csd_vddioq_h_n |
| + vccd vdda vddio_q vssa vssd vswitch |
| *.PININFO analog_en:I analog_pol:I analog_sel:I enable_vdda_h:I |
| *.PININFO enable_vswitch_h:I hld_i_h:I hld_i_h_n:I out:I vccd:I vdda:I |
| *.PININFO vddio_q:I vssa:I vssd:I vswitch:I enable_vdda_h_n:O |
| *.PININFO nga_amx_vswitch_h:O nga_pad_vswitch_h:O ngb_amx_vswitch_h:O |
| *.PININFO ngb_pad_vswitch_h:O nmida_vccd:O nmidb_vccd:O pd_csd_vswitch_h:O |
| *.PININFO pga_amx_vdda_h_n:O pga_pad_vddioq_h_n:O pgb_amx_vdda_h_n:O |
| *.PININFO pgb_pad_vddioq_h_n:O pu_csd_vddioq_h_n:O |
| XXamux_lv_decoder amuxbusa_on amuxbusa_on_n amuxbusb_on amuxbusb_on_n |
| + analog_en analog_pol analog_sel nga_pad_vswitch_h nga_pad_vswitch_h_n |
| + ngb_pad_vswitch_h ngb_pad_vswitch_h_n nmida_on_n nmida_vccd_n nmidb_on_n |
| + nmidb_vccd_n out pd_on pd_on_n pd_csd_vswitch_h_n pga_amx_vdda_h_n |
| + pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n pu_on pu_on_n |
| + pu_csd_vddioq_h_n vccd vssd / s130iom0_gpiov2_amux_decoder |
| XXamux_sw_drvr amux_en_vdda_h amux_en_vdda_h_n amux_en_vddio_h |
| + amux_en_vddio_h_n amux_en_vswitch_h amux_en_vswitch_h_n amuxbusa_on |
| + amuxbusa_on_n amuxbusb_on amuxbusb_on_n nga_amx_vswitch_h nga_pad_vswitch_h |
| + nga_pad_vswitch_h_n ngb_amx_vswitch_h ngb_pad_vswitch_h ngb_pad_vswitch_h_n |
| + nmida_on_n nmida_vccd nmida_vccd_n nmidb_on_n nmidb_vccd nmidb_vccd_n |
| + pd_csd_vswitch_h pd_csd_vswitch_h_n pd_on pd_on_n pga_amx_vdda_h_n |
| + pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n pu_csd_vddioq_h_n |
| + pu_on pu_on_n vccd vdda vddio_q vssa vssd vswitch / s130iom0_gpiov2_amux_drvr |
| XXamux_ls amux_en_vdda_h amux_en_vdda_h_n amux_en_vddio_h amux_en_vddio_h_n |
| + amux_en_vswitch_h amux_en_vswitch_h_n analog_en enable_vdda_h |
| + enable_vdda_h_n enable_vswitch_h hld_i_h hld_i_h_n vccd vdda vddio_q vssa |
| + vssd vswitch / s130iom0_gpiov2_amux_ls |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_amux |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_amux amuxbus_a amuxbus_b analog_en analog_pol |
| + analog_sel enable_vdda_h enable_vswitch_h hld_i_h hld_i_h_n out pad vccd |
| + vdda vddio_q vssa vssd vssio_q vswitch |
| *.PININFO analog_en:I analog_pol:I analog_sel:I enable_vdda_h:I |
| *.PININFO enable_vswitch_h:I hld_i_h:I hld_i_h_n:I out:I vccd:I vdda:I |
| *.PININFO vddio_q:I vssa:I vssd:I vssio_q:I vswitch:I amuxbus_a:B amuxbus_b:B |
| *.PININFO pad:B |
| DD3 vswitch vssd ddnw_sub_v5 area=570.0630 pj=97.150 m=1 |
| DD2 vdda vssd ddnw_sub_v5 area=946.9910 pj=155.390 m=1 |
| XXI28 net_184 net_18 / s130_esd_res75only_small |
| XXI54 pad net_184 / s130_esd_res75only_small |
| XXI26 pad net_201 / s130_esd_res75only_small |
| XXI27 pad net_202 / s130_esd_res75only_small |
| XXI55 pad pad / s130_esd_res75only_small |
| XXI53 pad pad / s130_esd_res75only_small |
| XXI58 net_170 net_222 / s130_esd_res75only_small |
| XXI57 pad net_170 / s130_esd_res75only_small |
| XXI39 pad net_198 / s130_esd_res75only_small |
| XXI40 pad net0287 / s130_esd_res75only_small |
| MmI52 net_198 pu_csd_vddioq_h_n vddio_q vddio_q pmos_v5 W=15 L=0.5 M=3 |
| MmMP_PU net0287 pu_csd_vddioq_h_n vddio_q vddio_q pmos_v5 W=15 L=0.5 M=4 |
| DD1 vswitch vssa dipw_dnw_v5 area=409.1940 pj=127.090 m=1 |
| DD0 vdda vssio_q dipw_dnw_v5 area=96.74720 pj=41.010 m=1 |
| DD4 vdda vssa dipw_dnw_v5 area=48.2080 pj=27.820 m=1 |
| XXmux_b amuxbus_b ngb_amx_vpmp_h ngb_pad_vpmp_h nmidb_vccd net_18 net_18 |
| + net_222 net_222 net_202 net_201 net_214 hld_i_h pgb_amx_vdda_h_n |
| + pgb_pad_vddioq_h_n vdda vddio_q vssa vssd / s130iom0_gpiov2_amux_switch |
| XXmux_a amuxbus_a nga_amx_vpmp_h nga_pad_vpmp_h nmida_vccd net_18 net_18 |
| + net_222 net_222 net_202 net_201 net_214 hld_i_h pga_amx_vdda_h_n |
| + pga_pad_vddioq_h_n vdda vddio_q vssa vssd / s130iom0_gpiov2_amux_switch |
| MmI49 net_198 pd_csd_vswitch_h vssio_q vssio_q nmos_v5 W=5 L=0.5 M=6 |
| MmMN_PD net0287 pd_csd_vswitch_h vssio_q vssio_q nmos_v5 W=5 L=0.5 M=8 |
| XXBBM_logic analog_en analog_pol analog_sel enable_vdda_h net_214 |
| + enable_vswitch_h hld_i_h hld_i_h_n nga_amx_vpmp_h nga_pad_vpmp_h |
| + ngb_amx_vpmp_h ngb_pad_vpmp_h nmida_vccd nmidb_vccd out pd_csd_vswitch_h |
| + pga_amx_vdda_h_n pga_pad_vddioq_h_n pgb_amx_vdda_h_n pgb_pad_vddioq_h_n |
| + pu_csd_vddioq_h_n vccd vdda vddio_q vssa vssd vswitch / |
| + s130iom0_gpiov2_amux_ctl_logic |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pudrvr_strong_slow |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pudrvr_strong_slow pad pu_h_n vcc_io vgnd_io vpb_drvr |
| *.PININFO pu_h_n:I vcc_io:I vgnd_io:I vpb_drvr:I pad:B |
| Mmpdrv pad pu_h_n vcc_io vpb_drvr pmos_v5 W=7 L=0.5 M=8 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pudrvr_weak |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pudrvr_weak pad pu_h_n vcc_io vgnd_io vpb_drvr |
| *.PININFO pu_h_n:I vcc_io:I vgnd_io:I vpb_drvr:I pad:B |
| Mmpdrv pad pu_h_n vcc_io vpb_drvr pmos_v5 W=7 L=0.5 M=4 |
| MmI29 pad pu_h_n vcc_io vpb_drvr pmos_v5 W=5 L=0.5 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_res_strong_slow |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_res_strong_slow ra rb vgnd_io |
| *.PININFO vgnd_io:I ra:B rb:B |
| RrI29 $PINS MINUS=net34 PLUS=net30 model=rpoly w=2 l=3 m=1 segments=1 |
| + rType=Parallel |
| Rrr1 $PINS MINUS=net30 PLUS=ra model=rpoly w=2 l=5 m=1 segments=1 |
| + rType=Parallel |
| RRM0 net30 net34 900.0u $[rm1] $W=1.32 $L=0.01 M=1 |
| RrI32 $PINS MINUS=rb PLUS=net34 model=rpoly w=2 l=2 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_res_weak |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_res_weak ra rb vgnd_io |
| *.PININFO vgnd_io:I ra:B rb:B |
| RrI85 $PINS MINUS=net1 PLUS=ra model=rpoly w=0.8 l=50.8 m=1 segments=1 |
| + rType=Parallel |
| RrI84 $PINS MINUS=net5 PLUS=net4 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI82 $PINS MINUS=net7 PLUS=net6 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI83 $PINS MINUS=net6 PLUS=net5 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI62 $PINS MINUS=rb PLUS=net7 model=rpoly w=0.8 l=1.5 m=1 segments=1 |
| + rType=Parallel |
| RrI104 $PINS MINUS=net4 PLUS=net3 model=rpoly w=0.8 l=6 m=1 segments=1 |
| + rType=Parallel |
| RrI134 $PINS MINUS=net3 PLUS=net2 model=rpoly w=0.8 l=6 m=1 segments=1 |
| + rType=Parallel |
| RRM1opt4 net6 net7 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM1opt3 net5 net6 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM1opt2 net4 net5 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM1opt5 net7 rb 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RRM1opt1 net3 net4 1.9m $[rm1] $W=0.66 $L=0.01 M=1 |
| RrI116 $PINS MINUS=net2 PLUS=net1 model=rpoly w=0.8 l=12 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pddrvr_weak |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pddrvr_weak pad pd_h vcc_io vgnd_io |
| *.PININFO pd_h:I vcc_io:I vgnd_io:I pad:B |
| Mmndrv1 pad pd_h vgnd_io vgnd_io nmos_v5 W=5 L=0.6 M=6 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pddrvr_strong_slow |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pddrvr_strong_slow pad pd_h vcc_io vgnd_io |
| *.PININFO pd_h:I vcc_io:I vgnd_io:I pad:B |
| Mmndrv pad pd_h vgnd_io vgnd_io nmos_v5 W=5 L=0.6 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_res250only_small |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_res250only_small pad rout |
| *.PININFO pad:B rout:B |
| RrI228 $PINS MINUS=rout PLUS=pad model=rpoly w=2 l=10.07 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pddrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pddrvr_strong pad pd_h<3> pd_h<2> pd_h_i2c tie_lo_esd |
| + vcc_io vgnd_io |
| *.PININFO pd_h<3>:I pd_h<2>:I pd_h_i2c:I vcc_io:I vgnd_io:I pad:O tie_lo_esd:O |
| RRM6 net_140 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM5 net_134 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM0 net_18 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM4 net_130 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net_124 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM3 net_142 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net_21 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| XXn12 pad pd_h_i2c vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<2> pad net_124 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<1> pad net_124 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<0> pad net_124 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<2> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<1> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<0> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<2> pad net_21 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<1> pad net_21 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<0> pad net_21 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<2> pad net_130 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<1> pad net_130 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<0> pad net_130 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<2> pad net_134 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<1> pad net_134 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<0> pad net_134 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<3> pad net_140 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<2> pad net_140 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<1> pad net_140 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<0> pad net_140 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn13 pad net_18 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn31 pad net_142 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXI49 vgnd_io tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| DD0 vcc_io vgnd_io dipw_dnw_v5 area=107.1740 pj=75.960 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_odrvr_sub |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_odrvr_sub force_hi_h_n pad pd_h<3> pd_h<2> pd_h<1> |
| + pd_h<0> pd_h_i2c pu_h_n<3> pu_h_n<2> pu_h_n<1> pu_h_n<0> tie_hi_esd |
| + tie_lo_esd vcc_io vgnd vgnd_io |
| *.PININFO force_hi_h_n:I pd_h<3>:I pd_h<2>:I pd_h<1>:I pd_h<0>:I pd_h_i2c:I |
| *.PININFO pu_h_n<3>:I pu_h_n<2>:I pu_h_n<1>:I pu_h_n<0>:I vcc_io:I vgnd:I |
| *.PININFO vgnd_io:I pad:O tie_hi_esd:B tie_lo_esd:B |
| XXstrong_slow_pudrvr strong_slow_pad pu_h_n<1> vcc_io vgnd vcc_io / |
| + s130iom0_com_pudrvr_strong_slow |
| XXpudrvr_weak weak_pad pu_h_n<0> vcc_io vgnd vcc_io / s130iom0_com_pudrvr_weak |
| XXres strong_slow_pad pad_r250 vgnd_io / s130iom0_com_res_strong_slow |
| XXres_weak weak_pad pad_r250 vgnd_io / s130iom0_com_res_weak |
| XXpddrvr_weak weak_pad pd_h<0> vcc_io vgnd_io / s130iom0_gpio_pddrvr_weak |
| XXstrong_slow_pddrvr strong_slow_pad pd_h<1> vcc_io vgnd_io / |
| + s130iom0_gpio_pddrvr_strong_slow |
| XXresd pad pad_r250 / s130_esd_res250only_small |
| DD0 vcc_io vgnd ddnw_sub_v5 area=2283.690 pj=218.670 m=1 |
| XXpudrvr_strong pad pu_h_n<3> pu_h_n<2> tie_hi_esd vcc_io vgnd / |
| + s130iom0_gpio_pudrvr_strong |
| XXpddrvr_strong pad pd_h<3> pd_h<2> pd_h_i2c tie_lo_esd vcc_io vgnd_io / |
| + s130iom0_gpiov2_pddrvr_strong |
| DD1 vcc_io vgnd_io dipw_dnw_v5 area=1649.5060 pj=241.680 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_odrvr |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_odrvr force_hi_h_n pad pd_h<3> pd_h<2> pd_h<1> pd_h<0> |
| + pd_h_i2c pu_h_n<3> pu_h_n<2> pu_h_n<1> pu_h_n<0> tie_hi_esd tie_lo_esd |
| + vcc_io vgnd vgnd_io |
| *.PININFO force_hi_h_n:I pd_h<3>:I pd_h<2>:I pd_h<1>:I pd_h<0>:I pd_h_i2c:I |
| *.PININFO pu_h_n<3>:I pu_h_n<2>:I pu_h_n<1>:I pu_h_n<0>:I vcc_io:I vgnd:I |
| *.PININFO vgnd_io:I pad:O tie_hi_esd:O tie_lo_esd:O |
| XXodrvr force_hi_h_n pad pd_h<3> pd_h<2> pd_h<1> pd_h<0> pd_h_i2c pu_h_n<3> |
| + pu_h_n<2> pu_h_n<1> pu_h_n<0> tie_hi_esd tie_lo_esd vcc_io vgnd vgnd_io / |
| + s130iom0_gpiov2_odrvr_sub |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pupredrvr_strong_slow |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pupredrvr_strong_slow drvhi_h pu_h_n puen_h vcc_io vgnd_io |
| *.PININFO drvhi_h:I puen_h:I vcc_io:I vgnd_io:I pu_h_n:O |
| MmI38 pu_h_n puen_h vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI37 pu_h_n drvhi_h vcc_io vcc_io pmos_v5 W=3 L=0.5 M=3 |
| MmI3 pu_h_n drvhi_h net17 vgnd_io nmos_v5 W=3 L=0.6 M=2 |
| MmI39 net17 puen_h vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pupredrvr_weak |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pupredrvr_weak drvhi_h pu_h_n puen_h vcc_io vgnd_io |
| *.PININFO drvhi_h:I puen_h:I vcc_io:I vgnd_io:I pu_h_n:O |
| MmI37 pu_h_n drvhi_h vcc_io vcc_io pmos_v5 W=5 L=0.6 M=2 |
| MmI38 pu_h_n puen_h vcc_io vcc_io pmos_v5 W=5 L=0.6 M=1 |
| MmI3 pu_h_n drvhi_h net21 vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI39 net21 puen_h vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pdpredrvr_weak |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pdpredrvr_weak drvlo_h_n pd_h pden_h_n vcc_io vgnd_io |
| *.PININFO drvlo_h_n:I pden_h_n:I vcc_io:I vgnd_io:I pd_h:O |
| MmI25 pd_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI26 pd_h pden_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI24 net25 pden_h_n vcc_io vcc_io pmos_v5 W=3 L=0.6 M=2 |
| MmI23 pd_h drvlo_h_n net25 vcc_io pmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pdpredrvr_strong_slow |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pdpredrvr_strong_slow drvlo_h_n pd_h pden_h_n vcc_io |
| + vgnd_io |
| *.PININFO drvlo_h_n:I pden_h_n:I vcc_io:I vgnd_io:I pd_h:O |
| MmI25 pd_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI26 pd_h pden_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI23 pd_h drvlo_h_n net25 vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI24 net25 pden_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pupredrvr_strong_nd2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pupredrvr_strong_nd2 drvhi_h en_fast<3> en_fast<2> |
| + en_fast<1> en_fast<0> pu_h_n puen_h vcc_io vgnd_io |
| *.PININFO drvhi_h:I en_fast<3>:I en_fast<2>:I en_fast<1>:I en_fast<0>:I |
| *.PININFO puen_h:I vcc_io:I vgnd_io:I pu_h_n:O |
| Mmmnin_fast<3> net_78 drvhi_h int<3> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| Mmmnin_fast<2> net_78 drvhi_h int<2> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| Mmmnin_fast<1> net_78 drvhi_h int<1> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| Mmmnin_fast<0> net_78 drvhi_h int<0> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| Rrrespu2 $PINS MINUS=int_res PLUS=pu_h_n model=rpoly w=0.33 l=4 m=1 segments=1 |
| + rType=Parallel |
| Rrrespu1 $PINS MINUS=net_78 PLUS=int_res model=rpoly w=0.33 l=11 m=1 |
| + segments=1 rType=Parallel |
| RRM0 pu_h_n net_78 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| Mmmpin pu_h_n drvhi_h vcc_io vcc_io pmos_v5 W=5 L=0.6 M=3 |
| Mmmnen_fast<3> int<3> en_fast<3> vgnd_io vgnd_io nmos_v5 W=1.5 L=1 M=1 |
| Mmmnen_fast<2> int<2> en_fast<2> vgnd_io vgnd_io nmos_v5 W=1.5 L=1 M=1 |
| Mmmnen_fast<1> int<1> en_fast<1> vgnd_io vgnd_io nmos_v5 W=1.5 L=1 M=1 |
| Mmmnen_fast<0> int<0> en_fast<0> vgnd_io vgnd_io nmos_v5 W=1.5 L=1 M=1 |
| Mmmpen pu_h_n puen_h vcc_io vcc_io pmos_v5 W=5 L=0.6 M=1 |
| Mmmnen_slow1 n<2> puen_h vgnd_io vgnd_io nmos_v5 W=0.42 L=4 M=1 |
| Mmmnin_slow pu_h_n drvhi_h n<2> vgnd_io nmos_v5 W=0.42 L=4 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_nand2_dnw |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_nand2_dnw in0 in1 out vgnd vpwr |
| *.PININFO in0:I in1:I vgnd:I vpwr:I out:O |
| MmI5 out in1 vpwr vpwr pmos_v5 W=3 L=0.6 M=1 |
| MmI3 out in0 vpwr vpwr pmos_v5 W=3 L=0.6 M=1 |
| MmI1 out in1 d vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI6 d in0 vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_inv_x1_dnw |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_inv_x1_dnw in out vgnd vpwr |
| *.PININFO in:I vgnd:I vpwr:I out:O |
| MmI1 out in vpwr vpwr pmos_v5 W=3 L=0.6 M=1 |
| MmI2 out in vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pupredrvr_nbias |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pupredrvr_nbias drvhi_h en_h en_h_n nbias pu_h_n puen_h |
| + vcc_io vgnd_io |
| *.PININFO drvhi_h:I en_h:I en_h_n:I pu_h_n:I puen_h:I vcc_io:I vgnd_io:I |
| *.PININFO nbias:O |
| MmI56 vcc_io pu_h_n net90 vcc_io pmos_v5 W=0.42 L=8 M=1 |
| RRM0 pu_h_n n<2> 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM3 nbias net049 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| RRM1 net081 n<6> 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| MmI50 n<1> puen_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI34 n<1> drvhi_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI30 bias_g drvhi_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI29 bias_g en_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI21 nbias bias_g vcc_io vcc_io pmos_v5 W=1 L=0.8 M=4 |
| MmI49 net049 bias_g vcc_io vcc_io pmos_v5 W=1 L=0.8 M=4 |
| MmI28 bias_g drvhi_h n<3> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| MmI27 n<3> n<2> n<4> vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| MmI26 n<4> en_h vgnd_io vgnd_io nmos_v5 W=1.5 L=0.5 M=1 |
| MmI24 nbias en_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.5 M=1 |
| MmI53 vgnd_io drvhi_i_h_n vccio_2vtn vgnd_io nmos_v5 W=3 L=0.5 M=1 |
| MmI25 nbias drvhi_i_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.5 M=1 |
| MmI12 drvhi_i_h_n drvhi_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=2 |
| MmI13 drvhi_i_h_n drvhi_h vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI40 vccio_2vtn vcc_io vgnd_io vgnd_io nmos_v5 W=0.42 L=8 M=1 |
| MmI19 n<6> n<6> vgnd_io vgnd_io nmos_v5 W=3 L=0.5 M=4 |
| MmI20 nbias nbias n<6> vgnd_io nmos_v5 W=3 L=0.5 M=4 |
| MmI39 net081 vccio_2vtn vgnd_io vgnd_io nmos_v5 W=3 L=0.5 M=4 |
| MmI54 net141 bias_g vgnd_io vgnd_io nmos_v5 W=0.42 L=4 M=1 |
| MmI41 n<7> n<7> n<8> vgnd_io nmos_v5 W=3 L=0.5 M=2 |
| MmI44 n<8> n<8> vccio_2vtn vgnd_io nmos_v5 W=3 L=0.5 M=2 |
| MmI32 n<1> n<2> n<2> vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI31 bias_g n<1> vcc_io vcc_io pmos_v5 W=3 L=0.5 M=4 |
| MmI47 n<7> bias_g vcc_io vcc_io pmos_v5 W=5 L=0.5 M=2 |
| RRM4 net141 nbias 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM2 bias_g net90 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pupredrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pupredrvr_strong drvhi_h pu_h_n<3> pu_h_n<2> puen_h |
| + slow_h_n vcc_io vgnd_io |
| *.PININFO drvhi_h:I puen_h:I slow_h_n:I vcc_io:I vgnd_io:I pu_h_n<3>:O |
| *.PININFO pu_h_n<2>:O |
| RRM3 vgnd_io en_fast_h_3<0> 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| RRM2 vgnd_io en_fast_h_3<1> 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| RRM1 en_fast_h_3<3> en_fast_h_3<2> 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| XXnd2a drvhi_h net_69 net_69 net_69 net_69 pu_h_n<2> puen_h vcc_io vgnd_io / |
| + s130iom0_gpiov2_pupredrvr_strong_nd2 |
| XXnd2b drvhi_h en_fast_h_3<3> en_fast_h_3<2> en_fast_h_3<1> en_fast_h_3<0> |
| + pu_h_n<3> puen_h vcc_io vgnd_io / s130iom0_gpiov2_pupredrvr_strong_nd2 |
| XXnand puen_h slow_h_n en_fast_h_n vgnd_io vcc_io / s130iom0_com_nand2_dnw |
| XXinv en_fast_h_n en_fast_h vgnd_io vcc_io / s130iom0_com_inv_x1_dnw |
| XXnbias drvhi_h en_fast_h en_fast_h_n nbias_out pu_h_n<2> puen_h vcc_io |
| + vgnd_io / s130iom0_com_pupredrvr_nbias |
| RRM5 nbias_out en_fast_h_3<3> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM6 nbias_out net_69 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pdpredrvr_strong_nr3 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pdpredrvr_strong_nr3 drvlo_h_n en_fast_n<1> |
| + en_fast_n<0> i2c_mode_h pd_h pden_h_n vcc_io vgnd_io |
| *.PININFO drvlo_h_n:I en_fast_n<1>:I en_fast_n<0>:I i2c_mode_h:I pden_h_n:I |
| *.PININFO vcc_io:I vgnd_io:I pd_h:O |
| MmI87<1> pd_h drvlo_h_n int2 vcc_io pmos_v5 W=0.42 L=0.5 M=1 |
| MmI87<0> pd_h drvlo_h_n int2 vcc_io pmos_v5 W=0.42 L=0.5 M=1 |
| MmI86<1> int2 en_fast_n<1> int1 vcc_io pmos_v5 W=0.42 L=0.5 M=1 |
| MmI86<0> int2 en_fast_n<0> int1 vcc_io pmos_v5 W=0.42 L=0.5 M=1 |
| MmI85 int1 i2c_mode_h vcc_io vcc_io pmos_v5 W=1 L=0.5 M=2 |
| Mmmpin_fast<1> pd_h drvlo_h_n int_nor<1> vcc_io pmos_v5 W=1.5 L=0.5 M=1 |
| Mmmpin_fast<0> pd_h drvlo_h_n int_nor<0> vcc_io pmos_v5 W=1.5 L=0.5 M=1 |
| Mmmpen_fast<1> int_nor<1> en_fast_n<1> vcc_io vcc_io pmos_v5 W=1.5 L=0.5 M=1 |
| Mmmpen_fast<0> int_nor<0> en_fast_n<0> vcc_io vcc_io pmos_v5 W=1.5 L=0.5 M=1 |
| Mmmpin_slow pd_h drvlo_h_n int_slow vcc_io pmos_v5 W=0.42 L=2 M=1 |
| MmI90 pd_h drvlo_h_n net43 vcc_io pmos_v5 W=0.42 L=2 M=1 |
| MmI56 net43 pden_h_n int1 vcc_io pmos_v5 W=0.42 L=2 M=1 |
| Mmmpen_slow int_slow pden_h_n vcc_io vcc_io pmos_v5 W=0.42 L=4 M=1 |
| Mmmnen pd_h pden_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=2 |
| Mmmnin pd_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=5 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pdpredrvr_strong_nr2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pdpredrvr_strong_nr2 drvlo_h_n en_fast_n<1> |
| + en_fast_n<0> i2c_mode_h pd_h pd_i2c_h pden_h_n vcc_io vgnd_io |
| *.PININFO drvlo_h_n:I en_fast_n<1>:I en_fast_n<0>:I i2c_mode_h:I pden_h_n:I |
| *.PININFO vcc_io:I vgnd_io:I pd_h:O pd_i2c_h:O |
| Mmmpin_fast<1> pd_i2c_h drvlo_h_n net_100 vcc_io pmos_v5 W=0.42 L=1 M=1 |
| Mmmpin_fast<0> pd_i2c_h drvlo_h_n net_100 vcc_io pmos_v5 W=0.42 L=1 M=1 |
| Mmmpen_fast1 net_100 en_fast_n<1> vcc_io vcc_io pmos_v5 W=0.42 L=1 M=1 |
| MmI77 pd_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=2 |
| Mmmnin pd_i2c_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=2 |
| MmI94 pd_h i2c_mode_h vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| Mmmnen pd_i2c_h pden_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI78 pd_h pden_h_n vgnd_io vgnd_io nmos_v5 W=3 L=0.6 M=1 |
| MmI73 net42 i2c_mode_h vcc_io vcc_io pmos_v5 W=3 L=0.5 M=3 |
| MmI72<1> net028<0> en_fast_n<1> net42 vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI72<0> net028<1> en_fast_n<0> net42 vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI76 pd_h drvlo_h_n net45 vcc_io pmos_v5 W=0.42 L=4 M=1 |
| MmI101 net45 pden_h_n net039 vcc_io pmos_v5 W=0.42 L=4 M=1 |
| MmI75 net039 pden_h_n net42 vcc_io pmos_v5 W=0.42 L=4 M=1 |
| Mmmpen_slow int_slow pden_h_n vcc_io vcc_io pmos_v5 W=0.42 L=4 M=1 |
| Mmmpin_slow pd_i2c_h drvlo_h_n int_slow vcc_io pmos_v5 W=0.42 L=4 M=1 |
| MmI74<1> pd_h drvlo_h_n net028<0> vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI74<0> pd_h drvlo_h_n net028<1> vcc_io pmos_v5 W=3 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_octl_mux |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_octl_mux a_h b_h sel_h sel_h_n vccio vssio y_h |
| *.PININFO a_h:I b_h:I sel_h:I sel_h_n:I vccio:I vssio:I y_h:O |
| MmI2 y_h sel_h b_h vccio pmos_v5 W=3 L=0.5 M=1 |
| MmI3 y_h sel_h_n a_h vccio pmos_v5 W=3 L=0.5 M=1 |
| MmI1 b_h sel_h_n y_h vssio nmos_v5 W=3 L=0.5 M=1 |
| MmI4 a_h sel_h y_h vssio nmos_v5 W=3 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_nor2_dnw |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_nor2_dnw in0 in1 out vgnd vpwr |
| *.PININFO in0:I in1:I vgnd:I vpwr:I out:O |
| MmI6 out in1 vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI1 out in0 vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI12 out in1 net17 vpwr pmos_v5 W=3 L=0.6 M=1 |
| MmI3 net17 in0 vpwr vpwr pmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_pdpredrvr_pbias |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_pdpredrvr_pbias drvlo_h_n en_h en_h_n pbias pd_h pden_h_n |
| + vcc_io vgnd_io |
| *.PININFO drvlo_h_n:I en_h:I en_h_n:I pd_h:I pden_h_n:I vcc_io:I vgnd_io:I |
| *.PININFO pbias:O |
| MmI47 pbias bias_g vgnd_io vgnd_io nmos_v5 W=1 L=1 M=2 |
| MmI36 net_159 bias_g vgnd_io vgnd_io nmos_v5 W=1 L=1 M=2 |
| RRM3 bias_g n<101> 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| RRM1 net_161 pbias 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| MmI20 bias_g n<1> vgnd_io vgnd_io nmos_v5 W=5 L=0.6 M=1 |
| MmI34 net157 bias_g vgnd_io vgnd_io nmos_v5 W=5 L=0.6 M=1 |
| MmI6 pbias en_h vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| MmI40 N0 drvlo_i_h vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| MmI14 pbias drvlo_i_h vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| MmI32 net161 net161 N0 vcc_io pmos_v5 W=5 L=0.5 M=4 |
| MmI31 net157 net157 net161 vcc_io pmos_v5 W=5 L=0.5 M=4 |
| MmI38 n<1> pden_h_n vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI24 n<1> drvlo_h_n vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI18 bias_g drvlo_h_n vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI19 bias_g en_h_n vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI13 drvlo_i_h drvlo_h_n vgnd_io vgnd_io nmos_v5 W=1 L=0.6 M=1 |
| MmI12 drvlo_i_h drvlo_h_n vcc_io vcc_io pmos_v5 W=1 L=0.5 M=2 |
| RRM0 net_168 pbias1 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| MmI33 N0 vgnd_io vcc_io vcc_io pmos_v5 W=0.42 L=8 M=1 |
| MmI44 pbias pbias pbias1 vcc_io pmos_v5 W=5 L=0.5 M=8 |
| MmI45 pbias1 pbias1 vcc_io vcc_io pmos_v5 W=5 L=0.5 M=8 |
| MmI30 net_168 N0 vcc_io vcc_io pmos_v5 W=5 L=0.5 M=8 |
| MmI43 net_161 bias_g vcc_io vcc_io pmos_v5 W=0.42 L=4 M=1 |
| MmI48 n<100> pd_h vgnd_io vgnd_io nmos_v5 W=0.42 L=4 M=1 |
| MmI41 n<101> pd_h n<100> vgnd_io nmos_v5 W=0.42 L=4 M=1 |
| MmI23 n<0> n<0> n<1> vgnd_io nmos_v5 W=3 L=0.5 M=1 |
| MmI16 net_158 n<0> net_157 vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI17 bias_g drvlo_h_n net_158 vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI15 net_157 en_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| RRM2 pbias net_159 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM4 pd_h n<0> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_pdpredrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_pdpredrvr_strong drvlo_h_n i2c_mode_h_n pd_h<4> |
| + pd_h<3> pd_h<2> pden_h_n slow_h tie_hi_esd vcc_io vgnd vgnd_io |
| *.PININFO drvlo_h_n:I i2c_mode_h_n:I pden_h_n:I slow_h:I tie_hi_esd:I vcc_io:I |
| *.PININFO vgnd:I vgnd_io:I pd_h<4>:O pd_h<3>:O pd_h<2>:O |
| MmI87 mod_drvlo_h_n_i2c pd_h<4> vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI88 mod_drvlo_h_n_i2c pd_h<4> vgnd vgnd nmos_v5 W=0.42 L=0.5 M=1 |
| XXI161 net_138 net_194 vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI93 i2c_mode_h_n i2c_mode_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI97 int_slow1 mod_slow_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXnr2 mod_drvlo_h_n en_fast2_n<1> en_fast2_n<0> mod_slow_h pd_h<3> pden_h_n |
| + vcc_io vgnd_io / s130iom0_gpiov2_pdpredrvr_strong_nr3 |
| XXnr3 drvlo_h_n pbias_out pbias_out mod_slow_h pd_h<2> pd_h<4> pden_h_n vcc_io |
| + vgnd_io / s130iom0_gpiov2_pdpredrvr_strong_nr2 |
| XXmux mod_drvlo_h_n_i2c drvlo_h_n i2c_mode_h i2c_mode_h_n vcc_io vgnd_io |
| + mod_drvlo_h_n / s130iom0_gpiov2_octl_mux |
| XXI160 i2c_mode_h_n slow_h net_138 vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI98 i2c_mode_h slow_h int_slow1 vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXnor net_194 pden_h_n en_fast_h vgnd_io vcc_io / s130iom0_com_nor2_dnw |
| XXinv en_fast_h en_fast_h_n vgnd_io vcc_io / s130iom0_com_inv_x1_dnw |
| XXbias drvlo_h_n en_fast_h en_fast_h_n pbias_out pd_h<4> pden_h_n vcc_io |
| + vgnd_io / s130iom0_com_pdpredrvr_pbias |
| RRM3 pbias_out net044 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM0 pbias_out en_fast2_n<1> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM2 vcc_io en_fast2_n<0> 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_obpredrvr |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_obpredrvr drvhi_h drvlo_h_n i2c_mode_h_n pd_h<4> |
| + pd_h<3> pd_h<2> pd_h<1> pd_h<0> pden_h_n<1> pden_h_n<0> pu_h_n<3> pu_h_n<2> |
| + pu_h_n<1> pu_h_n<0> puen_h<1> puen_h<0> slow_h slow_h_n tie_hi_esd vcc_io |
| + vgnd vgnd_io |
| *.PININFO drvhi_h:I drvlo_h_n:I i2c_mode_h_n:I pden_h_n<1>:I pden_h_n<0>:I |
| *.PININFO puen_h<1>:I puen_h<0>:I slow_h:I slow_h_n:I tie_hi_esd:I vcc_io:I |
| *.PININFO vgnd:I vgnd_io:I pd_h<4>:O pd_h<3>:O pd_h<2>:O pd_h<1>:O pd_h<0>:O |
| *.PININFO pu_h_n<3>:O pu_h_n<2>:O pu_h_n<1>:O pu_h_n<0>:O |
| DD1 vcc_io vgnd ddnw_sub_v5 area=1211.580 pj=164.720 m=1 |
| XXpu_strong_slow drvhi_h pu_h_n<1> puen_h<1> vcc_io vgnd_io / |
| + s130iom0_com_pupredrvr_strong_slow |
| XXpu_weak drvhi_h pu_h_n<0> puen_h<0> vcc_io vgnd_io / |
| + s130iom0_com_pupredrvr_weak |
| XXpd_weak drvlo_h_n pd_h<0> pden_h_n<0> vcc_io vgnd_io / |
| + s130iom0_com_pdpredrvr_weak |
| DD0 vcc_io vgnd_io dipw_dnw_v5 area=453.8420 pj=155.650 m=1 |
| XXpd_strong_slow drvlo_h_n pd_h<1> pden_h_n<1> vcc_io vgnd_io / |
| + s130iom0_com_pdpredrvr_strong_slow |
| XXpu_strong drvhi_h pu_h_n<3> pu_h_n<2> puen_h<1> slow_h_n vcc_io vgnd_io / |
| + s130iom0_gpiov2_pupredrvr_strong |
| XXpd_strong drvlo_h_n i2c_mode_h_n pd_h<4> pd_h<3> pd_h<2> pden_h_n<1> slow_h |
| + tie_hi_esd vcc_io vgnd vgnd_io / s130iom0_gpiov2_pdpredrvr_strong |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_hvsbt_xor |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_hvsbt_xor in0 in1 out vgnd vpwr |
| *.PININFO in0:I in1:I vgnd:I vpwr:I out:O |
| MmI17 net_14 in1 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI13 net_72 in1 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI12 out net_14 net_74 vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI5 out net_88 net_72 vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI18 net_88 in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI3 net_74 in0 vpwr vpwr pmos_v5 W=1 L=0.6 M=2 |
| MmI1 out in1 net_75 vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI14 net_75 in0 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI6 out net_14 net_73 vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI15 net_73 net_88 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI16 net_14 in1 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI19 net_88 in0 vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_octl |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_octl dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> |
| + dm_h_n<0> hld_i_h_n od_h pden_h_n<2> pden_h_n<1> pden_h_n<0> puen_0_h |
| + puen_2or1_h puen_h<1> puen_h<0> slow slow_h slow_h_n vcc_io vgnd vpwr |
| + vreg_en_h_n |
| *.PININFO dm_h<2>:I dm_h<1>:I dm_h<0>:I dm_h_n<2>:I dm_h_n<1>:I dm_h_n<0>:I |
| *.PININFO hld_i_h_n:I od_h:I slow:I vcc_io:I vgnd:I vpwr:I vreg_en_h_n:I |
| *.PININFO pden_h_n<2>:O pden_h_n<1>:O pden_h_n<0>:O puen_0_h:O puen_2or1_h:O |
| *.PININFO puen_h<1>:O puen_h<0>:O slow_h:O slow_h_n:O |
| XXI208 puen_2or1_h vreg_en_h_n n<5> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI187 dm_h<1> dm_h<0> n<3> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI203 n<10> dm_h<0> n<1> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI186 dm_h_n<2> dm_h_n<1> n<4> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI204 n<9> dm_h_n<0> n<0> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI185 dm_h_n<0> n<4> net_194 vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI382 dm_h<2> net_167 pden_h_n<2> vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI205 n<1> n<0> puen_2or1_h vgnd vcc_io / s130iom0_hvsbt_nand2 |
| XXI211 n<8> dm_h_n<1> puen_0_h vgnd vcc_io / s130iom0_hvsbt_nor |
| XXI201 dm_h_n<2> dm_h_n<1> n<9> vgnd vcc_io / s130iom0_hvsbt_nor |
| XXI381 dm_h<1> dm_h<0> net_167 vgnd vcc_io / s130iom0_hvsbt_nor |
| XXI254 puen_h1_n puen_h<1> vgnd vcc_io / s130iom0_hvsbt_inv_x2 |
| XXI256 puen_h0_n puen_h<0> vgnd vcc_io / s130iom0_hvsbt_inv_x2 |
| XXI247 pden_h1 pden_h_n<1> vgnd vcc_io / s130iom0_hvsbt_inv_x2 |
| XXI249 pden_h0 pden_h_n<0> vgnd vcc_io / s130iom0_hvsbt_inv_x2 |
| XXI209 n<5> n<2> vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI376 n<2> puen_h1_n vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI377 puen_0_h puen_h0_n vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI374 net_194 pden_h1 vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI375 n<3> pden_h0 vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| XXI210 dm_h<2> dm_h<0> n<8> vgnd vcc_io / s130iom0_hvsbt_xor |
| XXI200 dm_h<2> dm_h<1> n<10> vgnd vcc_io / s130iom0_hvsbt_xor |
| XXls_slow hld_i_h_n slow slow_h slow_h_n od_h vgnd vcc_io vgnd vpwr / |
| + s130iom0_com_ctl_ls |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_cclat_inv_in |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_cclat_inv_in in out vcc_io vgnd vnb |
| *.PININFO in:I vcc_io:I vgnd:I vnb:I out:O |
| Mmmp1 out in vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| Mmmn1 out in vgnd vnb nmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_cclat_inv_out |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_cclat_inv_out in out vcc_io vgnd vnb |
| *.PININFO in:I vcc_io:I vgnd:I vnb:I out:O |
| MmI1 out in vcc_io vcc_io pmos_v5 W=5 L=0.5 M=6 |
| MmI2 out in vgnd vnb nmos_v5 W=3 L=0.6 M=6 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_cclat_hvnand3 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_cclat_hvnand3 in0 in1 in2 out vcc_io vgnd vnb |
| *.PININFO in0:I in1:I in2:I vcc_io:I vgnd:I vnb:I out:O |
| Mmmp2 out in2 vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| Mmmp0 out in0 vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| Mmmp1 out in1 vcc_io vcc_io pmos_v5 W=5 L=0.5 M=1 |
| Mmmn0 n0 in0 vgnd vnb nmos_v5 W=3 L=0.6 M=4 |
| Mmmn2 out in2 n1 vnb nmos_v5 W=3 L=0.6 M=2 |
| Mmmn1 n1 in1 n0 vnb nmos_v5 W=3 L=0.6 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_cclat_hvnor3 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_cclat_hvnor3 in0 in1 in2 out vcc_io vgnd vnb |
| *.PININFO in0:I in1:I in2:I vcc_io:I vgnd:I vnb:I out:O |
| Mmmp2 out in2 n<1> vcc_io pmos_v5 W=5 L=0.5 M=4 |
| Mmmp1 n<1> in1 n<0> vcc_io pmos_v5 W=5 L=0.5 M=4 |
| Mmmn0 out in0 vgnd vnb nmos_v5 W=3 L=0.6 M=2 |
| Mmmn2 out in2 vgnd vnb nmos_v5 W=3 L=0.6 M=2 |
| Mmmn1 out in1 vgnd vnb nmos_v5 W=3 L=0.6 M=2 |
| Mmmp0 n<0> in0 vcc_io vcc_io pmos_v5 W=5 L=0.6 M=8 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_com_cclat |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_com_cclat drvhi_h drvlo_h_n oe_h_n pd_dis_h pu_dis_h vcc_io |
| + vgnd |
| *.PININFO oe_h_n:I pd_dis_h:I pu_dis_h:I vcc_io:I vgnd:I drvhi_h:O drvlo_h_n:O |
| XXinv_pudis pu_dis_h pu_dis_h_n vcc_io vgnd vgnd / s130iom0_com_cclat_inv_in |
| XXinv_oe1 oe_h_n oe_i_h vcc_io vgnd vgnd / s130iom0_com_cclat_inv_in |
| XXinv_oe2 oe_i_h oe_i_h_n vcc_io vgnd vgnd / s130iom0_com_cclat_inv_in |
| XXinv_out_1 n0 drvhi_h vcc_io vgnd vgnd / s130iom0_com_cclat_inv_out |
| XXinv_out n1 drvlo_h_n vcc_io vgnd vgnd / s130iom0_com_cclat_inv_out |
| XXnand3 oe_i_h drvlo_h_n pu_dis_h_n n0 vcc_io vgnd vgnd / |
| + s130iom0_com_cclat_hvnand3 |
| XXnor3 oe_i_h_n drvhi_h pd_dis_h n1 vcc_io vgnd vgnd / |
| + s130iom0_com_cclat_hvnor3 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_dat_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_dat_ls hld_h_n in out_h out_h_n rst_h set_h vcc_io vgnd |
| + vpwr_ka |
| *.PININFO hld_h_n:I in:I rst_h:I set_h:I vcc_io:I vgnd:I vpwr_ka:I out_h:O |
| *.PININFO out_h_n:O |
| MmI12 out_h fbk_n vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI13 out_h_n fbk vgnd vgnd nmos_v5 W=1 L=0.6 M=1 |
| MmI11 out_h fbk_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI14 out_h_n fbk vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI34 in_i_n in vgnd vgnd nmos W=1 L=0.25 M=2 |
| MmI35 in_i in_i_n vgnd vgnd nmos W=1 L=0.25 M=2 |
| MmI1 fbk_n fbk vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI2 fbk fbk_n vcc_io vcc_io pmos_v5 W=1 L=0.5 M=1 |
| MmI33 in_i in_i_n vpwr_ka vpwr_ka pmos_hvt W=3 L=0.25 M=1 |
| MmI32 in_i_n in vpwr_ka vpwr_ka pmos_hvt W=3 L=0.25 M=1 |
| MmI7 net095 in_i_n vgnd vgnd nmos_lvt W=1 L=0.15 M=8 |
| MmI8 net093 in_i vgnd vgnd nmos_lvt W=1 L=0.15 M=8 |
| MmI6 fbk_n hld_h_n net035 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI5 fbk hld_h_n net037 vgnd nmos_v5 W=5 L=0.5 M=1 |
| MmI31 net035 vpwr_ka net093 vgnd nmos_nat_v5 W=1 L=0.9 M=8 |
| MmI30 net037 vpwr_ka net095 vgnd nmos_nat_v5 W=1 L=0.9 M=8 |
| MmI3 fbk fbk_n vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| MmI4 fbk_n fbk vgnd vgnd nmos_v5 W=0.7 L=0.6 M=1 |
| Mmmnset fbk_n set_h vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| Mmmnrst fbk rst_h vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_opath_datoe |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_opath_datoe drvhi_h drvlo_h_n hld_h_n hld_i_ovr_h od_h |
| + oe_h oe_n out vcc_io vgnd vpwr_ka |
| *.PININFO hld_h_n:I hld_i_ovr_h:I od_h:I oe_n:I out:I vcc_io:I vgnd:I |
| *.PININFO vpwr_ka:I drvhi_h:O drvlo_h_n:O oe_h:O |
| XXcclat drvhi_h drvlo_h_n oe_h_n pd_dis_h pu_dis_h vcc_io vgnd / |
| + s130iom0_com_cclat |
| XXdat_ls hld_i_ovr_h out pd_dis_h pu_dis_h vgnd od_h vcc_io vgnd vpwr_ka / |
| + s130iom0_gpio_dat_ls |
| XXoe_ls hld_i_ovr_h oe_n oe_h_n oe_h vgnd od_h vcc_io vgnd vpwr_ka / |
| + s130iom0_gpio_dat_ls |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_octl_dat |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_octl_dat dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> |
| + dm_h_n<0> drvhi_h hld_i_h_n hld_i_ovr_h od_h oe_n out pd_h<4> pd_h<3> |
| + pd_h<2> pd_h<1> pd_h<0> pu_h_n<3> pu_h_n<2> pu_h_n<1> pu_h_n<0> slow |
| + slow_h_n tie_hi_esd vcc_io vgnd vgnd_io vpwr vpwr_ka |
| *.PININFO dm_h<2>:I dm_h<1>:I dm_h<0>:I dm_h_n<2>:I dm_h_n<1>:I dm_h_n<0>:I |
| *.PININFO hld_i_h_n:I hld_i_ovr_h:I od_h:I oe_n:I out:I slow:I tie_hi_esd:I |
| *.PININFO vcc_io:I vgnd:I vgnd_io:I vpwr:I vpwr_ka:I drvhi_h:O pd_h<4>:O |
| *.PININFO pd_h<3>:O pd_h<2>:O pd_h<1>:O pd_h<0>:O pu_h_n<3>:O pu_h_n<2>:O |
| *.PININFO pu_h_n<1>:O pu_h_n<0>:O slow_h_n:O |
| XXpredrvr drvhi_h drvlo_h_n pden_h_n<2> pd_h<4> pd_h<3> pd_h<2> pd_h<1> |
| + pd_h<0> pden_h_n<1> pden_h_n<0> pu_h_n<3> pu_h_n<2> pu_h_n<1> pu_h_n<0> |
| + puen_h<1> puen_h<0> slow_h slow_h_n tie_hi_esd vcc_io vgnd vgnd_io / |
| + s130iom0_gpiov2_obpredrvr |
| XXctl dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> dm_h_n<0> hld_i_h_n od_h |
| + pden_h_n<2> pden_h_n<1> pden_h_n<0> puen_0_h puen_2or1_h puen_h<1> puen_h<0> |
| + slow slow_h slow_h_n vcc_io vgnd vpwr vcc_io / s130iom0_gpiov2_octl |
| XXdatoe drvhi_h drvlo_h_n hld_i_h_n hld_i_ovr_h od_h oe_h oe_n out vcc_io vgnd |
| + vpwr_ka / s130iom0_gpiov2_opath_datoe |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_opath |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_opath dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> |
| + dm_h_n<0> hld_i_h_n hld_i_ovr_h od_h oe_n out pad slow tie_hi_esd tie_lo_esd |
| + vcc_io vgnd vgnd_io vpwr vpwr_ka |
| *.PININFO dm_h<2>:I dm_h<1>:I dm_h<0>:I dm_h_n<2>:I dm_h_n<1>:I dm_h_n<0>:I |
| *.PININFO hld_i_h_n:I hld_i_ovr_h:I od_h:I oe_n:I out:I slow:I vcc_io:I vgnd:I |
| *.PININFO vgnd_io:I vpwr:I vpwr_ka:I pad:O tie_hi_esd:O tie_lo_esd:O |
| XXodrvr net022 pad pd_h<3> pd_h<2> pd_h<1> pd_h<0> pd_h<4> pu_h_n<3> pu_h_n<2> |
| + pu_h_n<1> pu_h_n<0> tie_hi_esd tie_lo_esd vcc_io vgnd vgnd_io / |
| + s130iom0_gpiov2_odrvr |
| XXopath dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> dm_h_n<0> drvhi_h |
| + hld_i_h_n hld_i_ovr_h od_h oe_n out pd_h<4> pd_h<3> pd_h<2> pd_h<1> pd_h<0> |
| + pu_h_n<3> pu_h_n<2> pu_h_n<1> pu_h_n<0> slow slow_h_n tie_hi_esd vcc_io vgnd |
| + vgnd_io vpwr vpwr_ka / s130iom0_gpiov2_octl_dat |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_signal_5_sym_hv_local_5term |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_signal_5_sym_hv_local_5term gate in nbody nwellRing vgnd |
| *.PININFO gate:I in:B nbody:B nwellRing:B vgnd:B |
| MmI1 in gate vgnd nbody nmos_esd_v5 W=5.4 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_ovtv2_buf_localesd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_ovtv2_buf_localesd in_h out_h out_vt vddio_q vssd |
| + vtrip_sel_h |
| *.PININFO in_h:I vtrip_sel_h:I out_h:O out_vt:O vddio_q:B vssd:B |
| XXesd_res in_h out_h / s130_esd_res250only_small |
| XXggnfet1 vssd out_h vssd vddio_q vssd / s130_esd_signal_5_sym_hv_local_5term |
| XXggnfet6 vssd vddio_q vssd vddio_q out_h / |
| + s130_esd_signal_5_sym_hv_local_5term |
| Mmhv_passgate out_h vtrip_sel_h out_vt vssd nmos_v5 W=3 L=1 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_inbuf_lvinv_x1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_inbuf_lvinv_x1 in out vgnd vnb vpb vpwr |
| *.PININFO in:I vgnd:I vnb:I vpb:I vpwr:I out:O |
| MmI2 out in vgnd vnb nmos W=1 L=0.25 M=1 |
| MmI1 out in vpwr vpb pmos_hvt W=3 L=0.25 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_vcchib_in_buf |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_vcchib_in_buf in_h mode_vcchib_lv_n out out_n vcchib |
| + vssd |
| *.PININFO in_h:I mode_vcchib_lv_n:I vcchib:I vssd:I out:O out_n:O |
| MmI487 out out_n vssd vssd nmos W=1 L=0.25 M=3 |
| MmI549 net57 mode_vcchib_lv_n vcchib vcchib pmos W=5 L=0.25 M=1 |
| MmI429 out_n net81 vcchib vcchib pmos W=5 L=0.25 M=1 |
| MmI489 out out_n vcchib vcchib pmos W=5 L=0.25 M=1 |
| MmI423 out_n net81 vssd vssd nmos W=1 L=0.25 M=1 |
| MmI545 net_018 in_h fbk vssd nmos_v5 W=5 L=0.8 M=2 |
| MmI544 fbk in_h vssd vssd nmos_v5 W=5 L=0.8 M=2 |
| MmI424 net81 net_018 vssd vssd nmos W=1 L=0.25 M=2 |
| MmI541 net81 mode_vcchib_lv_n vssd vssd nmos W=1 L=0.25 M=2 |
| MmI420 net57 net_018 fbk vssd nmos_v5 W=1 L=0.8 M=3 |
| MmI436 net81 net_018 net112 vcchib pmos W=1 L=0.25 M=2 |
| MmI547 net108 mode_vcchib_lv_n vcchib vcchib pmos W=5 L=0.25 M=3 |
| MmI538 net112 mode_vcchib_lv_n vcchib vcchib pmos W=3 L=0.25 M=1 |
| MmI552 vssd vssd vssd vssd nmos_v5 W=1 L=0.8 M=1 |
| MmI551 vssd vssd vssd vssd nmos_v5 W=5 L=0.8 M=1 |
| MmI543 net_018 in_h net108 vcchib pmos_v5 W=5 L=0.8 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ipath_lvls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ipath_lvls in_vcchib in_vddio mode_normal_lv |
| + mode_normal_lv_n mode_vcchib_lv mode_vcchib_lv_n out out_b vcchib vssd |
| *.PININFO in_vcchib:I in_vddio:I mode_normal_lv:I mode_normal_lv_n:I |
| *.PININFO mode_vcchib_lv:I mode_vcchib_lv_n:I vcchib:I vssd:I out:O out_b:O |
| MmI342 net78 mode_normal_lv_n vcchib vcchib pmos W=3 L=0.25 M=2 |
| MmI340 net50 mode_vcchib_lv_n vcchib vcchib pmos W=3 L=0.25 M=2 |
| MmI343 out_b fbk net78 vcchib pmos W=3 L=0.25 M=2 |
| MmI336 out_b in_vcchib net50 vcchib pmos W=3 L=0.25 M=2 |
| MmI337 out out_b vcchib vcchib pmos W=3 L=0.25 M=4 |
| MmI351 net111 mode_normal_lv vssd vssd nmos W=3 L=0.25 M=2 |
| MmI350 out_b fbk net111 vssd nmos W=3 L=0.25 M=2 |
| MmI347 net95 mode_vcchib_lv vssd vssd nmos W=3 L=0.25 M=2 |
| MmI346 out_b in_vcchib net95 vssd nmos W=3 L=0.25 M=2 |
| MmI349 out out_b vssd vssd nmos W=3 L=0.25 M=2 |
| MmI339 fbk_n mode_normal_lv vcchib vcchib pmos W=5 L=0.25 M=1 |
| MmI338 fbk fbk_n vcchib vcchib pmos W=5 L=0.25 M=1 |
| MmI352 net115 mode_normal_lv vssd vssd nmos W=3 L=0.25 M=1 |
| MmI348 fbk fbk_n vssd vssd nmos W=3 L=0.25 M=1 |
| MmI345 fbk_n in_vddio vcchib vcchib pmos_v5 W=5 L=0.5 M=2 |
| MmI353 fbk_n in_vddio net115 vssd nmos_v5 W=1.5 L=0.5 M=1 |
| MmI341 out_b mode_normal_lv net70 vcchib pmos W=3 L=0.25 M=1 |
| MmI344 net70 mode_vcchib_lv vcchib vcchib pmos W=3 L=0.25 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ipath_hvls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ipath_hvls in_vcchib in_vddio inb_vcchib mode_normal |
| + mode_normal_n mode_vcchib mode_vcchib_n out out_b vddio_q vssd |
| *.PININFO in_vcchib:I in_vddio:I inb_vcchib:I mode_normal:I mode_normal_n:I |
| *.PININFO mode_vcchib:I mode_vcchib_n:I vddio_q:I vssd:I out:O out_b:O |
| MmI321 net75 mode_normal_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI318 net55 mode_vcchib_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI317 out_b net84 net55 vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI322 out_b in_vddio net75 vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI320 out out_b vddio_q vddio_q pmos_v5 W=5 L=0.5 M=5 |
| MmI325 fbk fbk_b vddio_q vddio_q pmos_v5 W=1.5 L=0.5 M=1 |
| MmI324 fbk_b fbk vddio_q vddio_q pmos_v5 W=1.5 L=0.5 M=1 |
| MmI336 net84 fbk_b vddio_q vddio_q pmos_v5 W=1.5 L=0.5 M=1 |
| MmI334 fbk inb_vcchib net116 vssd nmos_v5 W=5 L=0.5 M=3 |
| MmI329 fbk_b in_vcchib net92 vssd nmos_v5 W=5 L=0.5 M=3 |
| MmI331 out out_b vssd vssd nmos_v5 W=5 L=0.5 M=3 |
| MmI333 net116 mode_vcchib vssd vssd nmos_v5 W=5 L=0.5 M=4 |
| MmI327 net92 mode_vcchib vssd vssd nmos_v5 W=5 L=0.5 M=4 |
| MmI337 net84 fbk_b vssd vssd nmos_v5 W=1.5 L=0.5 M=1 |
| MmI328 fbk mode_vcchib_n vssd vssd nmos_v5 W=5 L=0.5 M=1 |
| MmI335 out_b net84 net88 vssd nmos_v5 W=3 L=0.5 M=1 |
| MmI326 net88 mode_vcchib vssd vssd nmos_v5 W=3 L=0.5 M=1 |
| MmI332 net112 mode_normal vssd vssd nmos_v5 W=3 L=0.5 M=1 |
| MmI330 out_b in_vddio net112 vssd nmos_v5 W=3 L=0.5 M=1 |
| MmI319 out_b mode_vcchib net63 vddio_q pmos_v5 W=5 L=0.5 M=1 |
| MmI323 net63 mode_normal vddio_q vddio_q pmos_v5 W=5 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_in_buf |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_in_buf in_h in_vt mode_normal_n out out_n vddio_q vssd |
| + vtrip_sel_h vtrip_sel_h_n |
| *.PININFO in_h:I in_vt:I mode_normal_n:I vddio_q:I vssd:I vtrip_sel_h:I |
| *.PININFO vtrip_sel_h_n:I out:O out_n:O |
| MmI644 vssd vssd vssd vssd nmos_v5 W=5 L=0.8 M=1 |
| MmI646 vssd vssd vssd vssd nmos_v5 W=5 L=0.8 M=1 |
| MmI588 fbk in_vt vssd vssd nmos_v5 W=5 L=0.8 M=1 |
| MmI592 net103 in_b fbk vssd nmos_v5 W=1 L=0.8 M=4 |
| MmI636 net158 mode_normal_cmos_h_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI597 fbk2 mode_normal_cmos_h_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI632 net122 mode_normal_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI600 net103 mode_normal_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=2 |
| MmI591 fbk in_h vssd vssd nmos_v5 W=5 L=0.8 M=6 |
| MmI647 vddio_q vddio_q vddio_q vddio_q pmos_v5 W=5 L=0.8 M=1 |
| MmI629 in_b in_h net158 vddio_q pmos_v5 W=5 L=0.8 M=1 |
| MmI631 in_b in_h net122 vddio_q pmos_v5 W=5 L=0.8 M=1 |
| MmI587 in_b in_h fbk vssd nmos_v5 W=5 L=0.8 M=5 |
| MmI590 fbk2 in_b fbk vssd nmos_v5 W=5 L=0.8 M=4 |
| MmI586 out_n net91 vssd vssd nmos_v5 W=5 L=0.5 M=1 |
| MmI642 out out_n vssd vssd nmos_v5 W=5 L=0.5 M=1 |
| MmI595 net138 mode_normal_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=1 |
| MmI596 out_n net91 vddio_q vddio_q pmos_v5 W=5 L=0.5 M=1 |
| MmI643 out out_n vddio_q vddio_q pmos_v5 W=5 L=0.5 M=1 |
| MmI598 net91 in_b net138 vddio_q pmos_v5 W=3 L=0.5 M=1 |
| MmI593 net91 mode_normal_n vssd vssd nmos_v5 W=3 L=0.5 M=2 |
| MmI589 net91 in_b vssd vssd nmos_v5 W=3 L=0.5 M=2 |
| MmI583 in_vt vtrip_sel_h_n vssd vssd nmos_v5 W=3 L=1 M=1 |
| XXI43 mode_normal_cmos_h mode_normal_cmos_h_n vssd vddio_q / |
| + s130iom0_hvsbt_inv_x1 |
| XXI488 vtrip_sel_h mode_normal_n mode_normal_cmos_h vssd vddio_q / |
| + s130iom0_hvsbt_nor |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ibuf_se |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ibuf_se enable_vddio_lv ibufmux_out ibufmux_out_h in_h |
| + in_vt mode_normal_n mode_vcchib_n vcchib vddio_q vssd vtrip_sel_h |
| + vtrip_sel_h_n |
| *.PININFO enable_vddio_lv:I in_h:I in_vt:I mode_normal_n:I mode_vcchib_n:I |
| *.PININFO vcchib:I vddio_q:I vssd:I vtrip_sel_h:I vtrip_sel_h_n:I |
| *.PININFO ibufmux_out:O ibufmux_out_h:O |
| XXI112 mode_normal_lv_n mode_normal_lv vssd vssd vcchib vcchib / |
| + s130iom0_gpiov2_inbuf_lvinv_x1 |
| XXI111 mode_vcchib_lv_n mode_vcchib_lv vssd vssd vcchib vcchib / |
| + s130iom0_gpiov2_inbuf_lvinv_x1 |
| XXI148 enable_vddio_lv mode_vcchib mode_vcchib_lv_n vssd vcchib / |
| + s130iom0_hvsbt_nand2 |
| XXI149 enable_vddio_lv mode_normal mode_normal_lv_n vssd vcchib / |
| + s130iom0_hvsbt_nand2 |
| XXI88 in_h mode_vcchib_lv_n out_vcchib out_n_vcchib vcchib vssd / |
| + s130iom0_gpiov2_vcchib_in_buf |
| XXI491 mode_normal_n mode_normal vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXI105 mode_vcchib_n mode_vcchib vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXlvls out_vcchib out_vddio mode_normal_lv mode_normal_lv_n mode_vcchib_lv |
| + mode_vcchib_lv_n ibufmux_out net57 vcchib vssd / s130iom0_gpiov2_ipath_lvls |
| XXhvls out_vcchib out_vddio out_n_vcchib mode_normal mode_normal_n mode_vcchib |
| + mode_vcchib_n ibufmux_out_h net68 vddio_q vssd / s130iom0_gpiov2_ipath_hvls |
| XXbuf in_h in_vt mode_normal_n out_vddio out_n_vddio vddio_q vssd vtrip_sel_h |
| + vtrip_sel_h_n / s130iom0_gpiov2_in_buf |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ictl_logic |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ictl_logic dm_h_n<2> dm_h_n<1> dm_h_n<0> ib_mode_sel_h |
| + ib_mode_sel_h_n inp_dis_h_n inp_dis_i_h inp_dis_i_h_n mode_normal_n |
| + mode_vcchib_n tripsel_i_h tripsel_i_h_n vddio_q vssd vtrip_sel_h_n |
| *.PININFO dm_h_n<2>:I dm_h_n<1>:I dm_h_n<0>:I ib_mode_sel_h:I |
| *.PININFO ib_mode_sel_h_n:I inp_dis_h_n:I vddio_q:I vssd:I vtrip_sel_h_n:I |
| *.PININFO inp_dis_i_h:O inp_dis_i_h_n:O mode_normal_n:O mode_vcchib_n:O |
| *.PININFO tripsel_i_h:O tripsel_i_h_n:O |
| XXI36 inp_dis_i_h_n ib_mode_sel_h mode_vcchib_n vssd vddio_q / |
| + s130iom0_hvsbt_nand2 |
| XXI35 inp_dis_i_h_n ib_mode_sel_h_n mode_normal_n vssd vddio_q / |
| + s130iom0_hvsbt_nand2 |
| XXI80 dm_buf_dis_n inp_dis_h_n inp_dis_i_h vssd vddio_q / s130iom0_hvsbt_nand2 |
| XXI79 dm_h_n<2> and_dm01 dm_buf_dis_n vssd vddio_q / s130iom0_hvsbt_nand2 |
| XXI78 dm_h_n<1> dm_h_n<0> nand_dm01 vssd vddio_q / s130iom0_hvsbt_nand2 |
| XXI74 tripsel_i_h tripsel_i_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXI111 inp_dis_i_h inp_dis_i_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXI75 nand_dm01 and_dm01 vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXI71 vtrip_sel_h_n mode_normal_n tripsel_i_h vssd vddio_q / s130iom0_hvsbt_nor |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiov2_ipath |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiov2_ipath dm_h_n<2> dm_h_n<1> dm_h_n<0> enable_vddio_lv |
| + ib_mode_sel_h ib_mode_sel_h_n inp_dis_h_n out out_h pad vcchib vddio_q vssd |
| + vtrip_sel_h_n |
| *.PININFO dm_h_n<2>:I dm_h_n<1>:I dm_h_n<0>:I enable_vddio_lv:I |
| *.PININFO ib_mode_sel_h:I ib_mode_sel_h_n:I inp_dis_h_n:I vcchib:I vddio_q:I |
| *.PININFO vssd:I vtrip_sel_h_n:I out:O out_h:O pad:B |
| XXI120 pad in_h in_vt vddio_q vssd tripsel_i_h / |
| + s130iom0_gpio_ovtv2_buf_localesd |
| XXI106 enable_vddio_lv out out_h in_h in_vt mode_normal_n mode_vcchib_n vcchib |
| + vddio_q vssd tripsel_i_h tripsel_i_h_n / s130iom0_gpiov2_ibuf_se |
| XXI107 dm_h_n<2> dm_h_n<1> dm_h_n<0> ib_mode_sel_h ib_mode_sel_h_n inp_dis_h_n |
| + en_h_n en_h mode_normal_n mode_vcchib_n tripsel_i_h tripsel_i_h_n vddio_q |
| + vssd vtrip_sel_h_n / s130iom0_gpiov2_ictl_logic |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_gpiov2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_gpiov2 amuxbus_a amuxbus_b analog_en analog_pol |
| + analog_sel dm<2> dm<1> dm<0> enable_h enable_inp_h enable_vdda_h |
| + enable_vddio enable_vswitch_h hld_h_n hld_ovr ib_mode_sel in in_h inp_dis |
| + oe_n out pad pad_a_esd_0_h pad_a_esd_1_h pad_a_noesd_h slow tie_hi_esd |
| + tie_lo_esd vccd vcchib vdda vddio vddio_q vssa vssd vssio vssio_q vswitch |
| + vtrip_sel |
| *.PININFO analog_en:I analog_pol:I analog_sel:I dm<2>:I dm<1>:I dm<0>:I |
| *.PININFO enable_h:I enable_inp_h:I enable_vdda_h:I enable_vddio:I |
| *.PININFO enable_vswitch_h:I hld_h_n:I hld_ovr:I ib_mode_sel:I inp_dis:I |
| *.PININFO oe_n:I out:I slow:I vtrip_sel:I in:O in_h:O tie_hi_esd:O |
| *.PININFO tie_lo_esd:O amuxbus_a:B amuxbus_b:B pad:B pad_a_esd_0_h:B |
| *.PININFO pad_a_esd_1_h:B pad_a_noesd_h:B vccd:B vcchib:B vdda:B vddio:B |
| *.PININFO vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| RRM0 pad pad_a_noesd_h 100.0u $[rm4] $W=12.37 $L=0.035 M=1 |
| XXresd3 pad_a_esd_1_h net_129 / s130_esd_res75only_small |
| XXresd4 net_129 pad / s130_esd_res75only_small |
| XXresd1 net_130 pad / s130_esd_res75only_small |
| XXresd2 pad_a_esd_0_h net_130 / s130_esd_res75only_small |
| XXctrl dm<2> dm<1> dm<0> dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> dm_h_n<0> |
| + enable_h enable_inp_h hld_h_n hld_i_h hld_i_h_n hld_i_ovr_h hld_ovr |
| + ib_mode_sel ib_mode_sel_h ib_mode_sel_h_n inp_dis inp_dis_h_n od_i_h vddio_q |
| + vssd vccd vtrip_sel vtrip_sel_h vtrip_sel_h_n / s130iom0_gpiov2_ctl |
| XXamux amuxbus_a amuxbus_b analog_en analog_pol analog_sel enable_vdda_h |
| + enable_vswitch_h hld_i_h hld_i_h_n out pad vccd vdda vddio_q vssa vssd |
| + vssio_q vswitch / s130iom0_gpiov2_amux |
| XXopath dm_h<2> dm_h<1> dm_h<0> dm_h_n<2> dm_h_n<1> dm_h_n<0> hld_i_h_n |
| + hld_i_ovr_h od_i_h oe_n out pad slow tie_hi_esd tie_lo_esd vddio vssd vssio |
| + vccd vcchib / s130iom0_gpiov2_opath |
| XXipath dm_h_n<2> dm_h_n<1> dm_h_n<0> enable_vddio ib_mode_sel_h |
| + ib_mode_sel_h_n inp_dis_h_n in in_h pad vcchib vddio_q vssd vtrip_sel_h_n / |
| + s130iom0_gpiov2_ipath |
| RrS0 pad pad_a_noesd_h 100.0u $[rm3] $W=12.37 $L=0.035 M=1 |
| XPAD0 pad pad_bond w=60 l=70 m=1 |
| RRM1 pad pad_a_noesd_h 1.5m $[rm3] $W=1.07 $L=0.035 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_ctl |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_ctl enable_h hld_h_n sel<4> sel<3> sel<2> sel<1> |
| + sel<0> sel_h<4> sel_h<3> sel_h<2> sel_h<1> sel_h<0> selb_h<4> selb_h<3> |
| + selb_h<2> selb_h<1> selb_h<0> vccd vddio_q vrefgen_en vrefgen_en_h |
| + vrefgen_en_h_n vssd |
| *.PININFO enable_h:I hld_h_n:I sel<4>:I sel<3>:I sel<2>:I sel<1>:I sel<0>:I |
| *.PININFO vccd:I vddio_q:I vrefgen_en:I vssd:I sel_h<4>:O sel_h<3>:O |
| *.PININFO sel_h<2>:O sel_h<1>:O sel_h<0>:O selb_h<4>:O selb_h<3>:O selb_h<2>:O |
| *.PININFO selb_h<1>:O selb_h<0>:O vrefgen_en_h:O vrefgen_en_h_n:O |
| XXI353 hld_i_h_n vrefgen_en vrefgen_en_h vrefgen_en_h_n enable_h_n vssd |
| + vddio_q vssd vccd / s130iom0_com_ctl_ls |
| XXls<4> hld_i_h_n sel<4> sel_h<4> selb_h<4> enable_h_n vssd vddio_q vssd vccd |
| + / s130iom0_com_ctl_ls |
| XXls<3> hld_i_h_n sel<3> sel_h<3> selb_h<3> enable_h_n vssd vddio_q vssd vccd |
| + / s130iom0_com_ctl_ls |
| XXls<2> hld_i_h_n sel<2> sel_h<2> selb_h<2> enable_h_n vssd vddio_q vssd vccd |
| + / s130iom0_com_ctl_ls |
| XXls<1> hld_i_h_n sel<1> sel_h<1> selb_h<1> enable_h_n vssd vddio_q vssd vccd |
| + / s130iom0_com_ctl_ls |
| XXls<0> hld_i_h_n sel<0> sel_h<0> selb_h<0> enable_h_n vssd vddio_q vssd vccd |
| + / s130iom0_com_ctl_ls |
| XXI50 enable_h enable_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXhld_i_h_inv1 net1 hld_i_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXhld_nand enable_h hld_h_n net1 vssd vddio_q / s130iom0_hvsbt_nand2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_hv_inv |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_hv_inv in out vddio_q vssd |
| *.PININFO in:I vddio_q:I vssd:I out:O |
| MmI279 out in vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI277 out in vssd vssd nmos_v5 W=0.75 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_hv_nor2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_hv_nor2 in1 in2 out vddio_q vssd |
| *.PININFO in1:I in2:I vddio_q:I vssd:I out:O |
| MmI277 out in1 vssd vssd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI293 out in2 vssd vssd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI279 out in1 net10 vddio_q pmos_v5 W=1 L=0.5 M=2 |
| MmI292 net10 in2 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_hv_nand2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_hv_nand2 in1 in2 out vddio_q vssd |
| *.PININFO in1:I in2:I vddio_q:I vssd:I out:O |
| MmI280 out in2 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI279 out in1 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI277 out in1 net19 vssd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI278 net19 in2 vssd vssd nmos_v5 W=0.75 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_hv_nand3 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_hv_nand3 in1 in2 in3 out vddio_q vssd |
| *.PININFO in1:I in2:I in3:I vddio_q:I vssd:I out:O |
| MmI280 out in2 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI281 out in3 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI279 out in1 vddio_q vddio_q pmos_v5 W=1 L=0.5 M=1 |
| MmI277 out in1 net27 vssd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI278 net27 in2 net31 vssd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI282 net31 in3 vssd vssd nmos_v5 W=0.75 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_decoder_5_32_cell |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_decoder_5_32_cell in0 in1 in2 in3 in4 vddio_q |
| + vrefin vrefout vssd |
| *.PININFO in0:I in1:I in2:I in3:I in4:I vddio_q:I vssd:I vrefin:B vrefout:B |
| MmI283 vrefout net33 vrefin vddio_q pmos_v5 W=1 L=0.5 M=3 |
| XXI280 switch_en net33 vddio_q vssd / s130iom0_gpiovrefv2_hv_inv |
| MmI294 vrefin switch_en vrefout vssd nmos_v5 W=0.75 L=0.5 M=4 |
| XXI277 net43 net012 switch_en vddio_q vssd / s130iom0_gpiovrefv2_hv_nor2 |
| XXI279 in3 in4 net012 vddio_q vssd / s130iom0_gpiovrefv2_hv_nand2 |
| XXI278 in0 in1 in2 net43 vddio_q vssd / s130iom0_gpiovrefv2_hv_nand3 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_decoder_5_32 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_decoder_5_32 sel_h<4> sel_h<3> sel_h<2> sel_h<1> |
| + sel_h<0> selb_h<4> selb_h<3> selb_h<2> selb_h<1> selb_h<0> vddio_q vref<31> |
| + vref<30> vref<29> vref<28> vref<27> vref<26> vref<25> vref<24> vref<23> |
| + vref<22> vref<21> vref<20> vref<19> vref<18> vref<17> vref<16> vref<15> |
| + vref<14> vref<13> vref<12> vref<11> vref<10> vref<9> vref<8> vref<7> vref<6> |
| + vref<5> vref<4> vref<3> vref<2> vref<1> vref<0> vrefin vssd |
| *.PININFO sel_h<4>:I sel_h<3>:I sel_h<2>:I sel_h<1>:I sel_h<0>:I selb_h<4>:I |
| *.PININFO selb_h<3>:I selb_h<2>:I selb_h<1>:I selb_h<0>:I vddio_q:I vssd:I |
| *.PININFO vref<31>:B vref<30>:B vref<29>:B vref<28>:B vref<27>:B vref<26>:B |
| *.PININFO vref<25>:B vref<24>:B vref<23>:B vref<22>:B vref<21>:B vref<20>:B |
| *.PININFO vref<19>:B vref<18>:B vref<17>:B vref<16>:B vref<15>:B vref<14>:B |
| *.PININFO vref<13>:B vref<12>:B vref<11>:B vref<10>:B vref<9>:B vref<8>:B |
| *.PININFO vref<7>:B vref<6>:B vref<5>:B vref<4>:B vref<3>:B vref<2>:B |
| *.PININFO vref<1>:B vref<0>:B vrefin:B |
| XXI287 sel_h<0> selb_h<1> selb_h<2> selb_h<3> selb_h<4> vddio_q vref<1> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI277 selb_h<0> selb_h<1> selb_h<2> selb_h<3> selb_h<4> vddio_q vref<0> |
| + vrefin vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI289 sel_h<0> sel_h<1> selb_h<2> selb_h<3> selb_h<4> vddio_q vref<3> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI288 selb_h<0> sel_h<1> selb_h<2> selb_h<3> selb_h<4> vddio_q vref<2> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI333 sel_h<0> selb_h<1> selb_h<2> sel_h<3> selb_h<4> vddio_q vref<9> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI332 selb_h<0> selb_h<1> selb_h<2> sel_h<3> selb_h<4> vddio_q vref<8> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI331 sel_h<0> sel_h<1> selb_h<2> sel_h<3> selb_h<4> vddio_q vref<11> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI330 selb_h<0> sel_h<1> selb_h<2> sel_h<3> selb_h<4> vddio_q vref<10> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI329 selb_h<0> sel_h<1> sel_h<2> sel_h<3> selb_h<4> vddio_q vref<14> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI328 sel_h<0> sel_h<1> sel_h<2> sel_h<3> selb_h<4> vddio_q vref<15> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI327 selb_h<0> selb_h<1> sel_h<2> sel_h<3> selb_h<4> vddio_q vref<12> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI349 selb_h<0> selb_h<1> sel_h<2> sel_h<3> sel_h<4> vddio_q vref<28> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI326 sel_h<0> selb_h<1> sel_h<2> sel_h<3> selb_h<4> vddio_q vref<13> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI321 selb_h<0> sel_h<1> sel_h<2> selb_h<3> selb_h<4> vddio_q vref<6> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI322 sel_h<0> sel_h<1> sel_h<2> selb_h<3> selb_h<4> vddio_q vref<7> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI323 selb_h<0> selb_h<1> sel_h<2> selb_h<3> selb_h<4> vddio_q vref<4> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI324 sel_h<0> selb_h<1> sel_h<2> selb_h<3> selb_h<4> vddio_q vref<5> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI358 sel_h<0> selb_h<1> selb_h<2> selb_h<3> sel_h<4> vddio_q vref<17> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI357 selb_h<0> selb_h<1> selb_h<2> selb_h<3> sel_h<4> vddio_q vref<16> |
| + vrefin vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI356 sel_h<0> sel_h<1> selb_h<2> selb_h<3> sel_h<4> vddio_q vref<19> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI355 selb_h<0> sel_h<1> selb_h<2> selb_h<3> sel_h<4> vddio_q vref<18> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI354 selb_h<0> sel_h<1> sel_h<2> selb_h<3> sel_h<4> vddio_q vref<22> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI353 sel_h<0> sel_h<1> sel_h<2> selb_h<3> sel_h<4> vddio_q vref<23> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI352 selb_h<0> selb_h<1> sel_h<2> selb_h<3> sel_h<4> vddio_q vref<20> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI351 sel_h<0> selb_h<1> sel_h<2> selb_h<3> sel_h<4> vddio_q vref<21> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI350 sel_h<0> selb_h<1> sel_h<2> sel_h<3> sel_h<4> vddio_q vref<29> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI343 sel_h<0> selb_h<1> selb_h<2> sel_h<3> sel_h<4> vddio_q vref<25> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI344 selb_h<0> selb_h<1> selb_h<2> sel_h<3> sel_h<4> vddio_q vref<24> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI345 sel_h<0> sel_h<1> selb_h<2> sel_h<3> sel_h<4> vddio_q vref<27> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI346 selb_h<0> sel_h<1> selb_h<2> sel_h<3> sel_h<4> vddio_q vref<26> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI347 selb_h<0> sel_h<1> sel_h<2> sel_h<3> sel_h<4> vddio_q vref<30> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| XXI348 sel_h<0> sel_h<1> sel_h<2> sel_h<3> sel_h<4> vddio_q vref<31> vrefin |
| + vssd / s130iom0_gpiovrefv2_decoder_5_32_cell |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpiovrefv2_res_ladder |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpiovrefv2_res_ladder vddio_q vref<31> vref<30> vref<29> |
| + vref<28> vref<27> vref<26> vref<25> vref<24> vref<23> vref<22> vref<21> |
| + vref<20> vref<19> vref<18> vref<17> vref<16> vref<15> vref<14> vref<13> |
| + vref<12> vref<11> vref<10> vref<9> vref<8> vref<7> vref<6> vref<5> vref<4> |
| + vref<3> vref<2> vref<1> vref<0> vrefgen_en_h vrefgen_en_h_n vssd |
| *.PININFO vddio_q:I vrefgen_en_h:I vrefgen_en_h_n:I vssd:I vref<31>:O |
| *.PININFO vref<30>:O vref<29>:O vref<28>:O vref<27>:O vref<26>:O vref<25>:O |
| *.PININFO vref<24>:O vref<23>:O vref<22>:O vref<21>:O vref<20>:O vref<19>:O |
| *.PININFO vref<18>:O vref<17>:O vref<16>:O vref<15>:O vref<14>:O vref<13>:O |
| *.PININFO vref<12>:O vref<11>:O vref<10>:O vref<9>:O vref<8>:O vref<7>:O |
| *.PININFO vref<6>:O vref<5>:O vref<4>:O vref<3>:O vref<2>:O vref<1>:O vref<0>:O |
| RrI163 $PINS B=vssd MINUS=vref<25> PLUS=vref<26> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI158 $PINS B=vssd MINUS=vref<27> PLUS=vref<28> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI209 $PINS B=vssd MINUS=vref<8> PLUS=vref<7> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI162 $PINS B=vssd MINUS=vref<26> PLUS=vref<27> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI197 $PINS B=vssd MINUS=vref<19> PLUS=vref<18> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI160 $PINS B=vssd MINUS=vref<29> PLUS=vref<30> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI161 $PINS B=vssd MINUS=vref<30> PLUS=vref<31> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI196 $PINS B=vssd MINUS=vref<18> PLUS=vref<17> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI213 $PINS B=vssd MINUS=vref<3> PLUS=vref<2> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI198 $PINS B=vssd MINUS=vref<20> PLUS=vref<19> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI215 $PINS B=vssd MINUS=vref<5> PLUS=vref<4> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI199 $PINS B=vssd MINUS=vref<21> PLUS=vref<20> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI201 $PINS B=vssd MINUS=vref<15> PLUS=vref<16> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI212 $PINS B=vssd MINUS=vref<2> PLUS=vref<1> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI195 $PINS B=vssd MINUS=vref<22> PLUS=vref<21> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI193 $PINS B=vssd MINUS=vref<24> PLUS=vref<23> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI194 $PINS B=vssd MINUS=vref<23> PLUS=vref<22> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI207 $PINS B=vssd MINUS=vref<9> PLUS=vref<10> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI164 $PINS B=vssd MINUS=vref<24> PLUS=vref<25> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI204 $PINS B=vssd MINUS=vref<13> PLUS=vref<14> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI205 $PINS B=vssd MINUS=vref<14> PLUS=vref<15> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI206 $PINS B=vssd MINUS=vref<10> PLUS=vref<11> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI159 $PINS B=vssd MINUS=vref<28> PLUS=vref<29> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI200 $PINS B=vssd MINUS=vref<17> PLUS=vref<16> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI214 $PINS B=vssd MINUS=vref<4> PLUS=vref<3> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI216 $PINS B=vssd MINUS=vref<1> PLUS=vref<0> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI210 $PINS B=vssd MINUS=vref<7> PLUS=vref<6> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI211 $PINS B=vssd MINUS=vref<6> PLUS=vref<5> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI202 $PINS B=vssd MINUS=vref<11> PLUS=vref<12> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI208 $PINS B=vssd MINUS=vref<8> PLUS=vref<9> model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| RrI203 $PINS B=vssd MINUS=vref<12> PLUS=vref<13> model=rndiff_v5 w=0.29 |
| + l=350.38 m=1 segments=1 rType=Parallel |
| RrI157 $PINS B=vssd MINUS=vref<31> PLUS=net81 model=rndiff_v5 w=0.29 l=350.38 |
| + m=1 segments=1 rType=Parallel |
| MmI150 net81 vrefgen_en_h_n vddio_q vddio_q pmos_v5 W=3 L=0.5 M=10 |
| MmI190 net99 vrefgen_en_h net29 vssd nmos_v5 W=3 L=0.5 M=10 |
| MmI191 net29 vrefgen_en_h vssd vssd nmos_v5 W=3 L=0.5 M=10 |
| RrI192 $PINS B=vssd MINUS=net37 PLUS=net99 model=rndiff_v5 w=0.29 l=2480.98 |
| + m=1 segments=1 rType=Parallel |
| RrI378 $PINS B=vssd MINUS=vref<0> PLUS=net37 model=rndiff_v5 w=0.29 l=2480.98 |
| + m=1 segments=1 rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_gpiovrefv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_gpiovrefv2 amuxbus_a amuxbus_b enable_h hld_h_n |
| + ref_sel<4> ref_sel<3> ref_sel<2> ref_sel<1> ref_sel<0> vccd vcchib vdda |
| + vddio vddio_q vinref vrefgen_en vssa vssd vssio vssio_q vswitch |
| *.PININFO enable_h:I hld_h_n:I ref_sel<4>:I ref_sel<3>:I ref_sel<2>:I |
| *.PININFO ref_sel<1>:I ref_sel<0>:I vrefgen_en:I amuxbus_a:B amuxbus_b:B |
| *.PININFO vccd:B vcchib:B vdda:B vddio:B vddio_q:B vinref:B vssa:B vssd:B |
| *.PININFO vssio:B vssio_q:B vswitch:B |
| XXI391 enable_h hld_h_n ref_sel<4> ref_sel<3> ref_sel<2> ref_sel<1> ref_sel<0> |
| + sel_h<4> sel_h<3> sel_h<2> sel_h<1> sel_h<0> selb_h<4> selb_h<3> selb_h<2> |
| + selb_h<1> selb_h<0> vccd vddio_q vrefgen_en vrefgen_en_h vrefgen_en_h_n vssd |
| + / s130iom0_gpiovrefv2_ctl |
| XXI397 sel_h<4> sel_h<3> sel_h<2> sel_h<1> sel_h<0> selb_h<4> selb_h<3> |
| + selb_h<2> selb_h<1> selb_h<0> vddio_q vref<31> vref<30> vref<29> vref<28> |
| + vref<27> vref<26> vref<25> vref<24> vref<23> vref<22> vref<21> vref<20> |
| + vref<19> vref<18> vref<17> vref<16> vref<15> vref<14> vref<13> vref<12> |
| + vref<11> vref<10> vref<9> vref<8> vref<7> vref<6> vref<5> vref<4> vref<3> |
| + vref<2> vref<1> vref<0> vinref vssd / s130iom0_gpiovrefv2_decoder_5_32 |
| XXI376 vddio_q vref<31> vref<30> vref<29> vref<28> vref<27> vref<26> vref<25> |
| + vref<24> vref<23> vref<22> vref<21> vref<20> vref<19> vref<18> vref<17> |
| + vref<16> vref<15> vref<14> vref<13> vref<12> vref<11> vref<10> vref<9> |
| + vref<8> vref<7> vref<6> vref<5> vref<4> vref<3> vref<2> vref<1> vref<0> |
| + vrefgen_en_h vrefgen_en_h_n vssd / s130iom0_gpiovrefv2_res_ladder |
| MmI276 vinref vrefgen_en_h_n vssd vssd nmos_v5 W=3 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_ground_hvc_wpad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_ground_hvc_wpad amuxbus_a amuxbus_b drn_hvc g_core g_pad |
| + ogc_hvc src_bdy_hvc vccd vcchib vdda vddio vddio_q vssa vssd vssio vssio_q |
| + vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B drn_hvc:B g_core:B g_pad:B ogc_hvc:B |
| *.PININFO src_bdy_hvc:B vccd:B vcchib:B vdda:B vddio:B vddio_q:B vssa:B vssd:B |
| *.PININFO vssio:B vssio_q:B vswitch:B |
| Mmnc2 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=4 M=5 |
| Mmnc1 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=8 M=15 |
| DD0 vddio vssd ddnw_sub_v5 area=10358.70 pj=619.080 m=1 |
| Mmcxtor2 drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=10 L=0.5 M=22 |
| Mmpre_n1 g_nclamp g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=7 L=0.5 M=15 |
| Mmclamp_xtor drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=20 L=0.5 M=120 |
| Mmpre_p1 g_nclamp g_pdpre drn_hvc drn_hvc pmos_v5 W=7 L=0.5 M=50 |
| DD1 vddio src_bdy_hvc dipw_dnw_v5 area=9495.080 pj=653.940 m=1 |
| XPAD0 g_pad pad_bond w=60 l=70 m=1 |
| RrI13 g_pad g_core 600.0u $[rm3] $W=23.9 $L=0.3 M=2 |
| Rrrc_res $PINS MINUS=g_pdpre PLUS=net90 model=rpoly w=0.33 l=470.66 m=1 |
| + segments=1 rType=Series |
| RrI38 $PINS MINUS=net94 PLUS=drn_hvc model=rpoly w=0.33 l=703.63 m=1 |
| + segments=1 rType=Series |
| RrI37 $PINS MINUS=net90 PLUS=net94 model=rpoly w=0.33 l=1552.97 m=1 segments=1 |
| + rType=Series |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_gnd2gnd_120x2_lv_isosub |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_gnd2gnd_120x2_lv_isosub vssi vssn vsub |
| *.PININFO vssi:B vssn:B vsub:B |
| DD0 vssi vssn dpsd_nw_esd area=22.5 pj=33 m=4 |
| DD1 vssn vssi dpsd_nw_esd area=22.5 pj=33 m=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_ground_lvc_wpad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_ground_lvc_wpad amuxbus_a amuxbus_b bdy2_b2b drn_lvc1 |
| + drn_lvc2 g_core g_pad ogc_lvc src_bdy_lvc1 src_bdy_lvc2 vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B bdy2_b2b:B drn_lvc1:B drn_lvc2:B g_core:B |
| *.PININFO g_pad:B ogc_lvc:B src_bdy_lvc1:B src_bdy_lvc2:B vccd:B vcchib:B |
| *.PININFO vdda:B vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| RrI44 $PINS MINUS=net161 PLUS=drn_lvc2 model=rpoly w=0.33 l=901.32 m=1 |
| + segments=1 rType=Series |
| Mmclamp_xtor drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=166 |
| MmI40 g_nclamp_lvc2 g_pdpre_lvc2 drn_lvc2 drn_lvc2 pmos W=7 L=0.18 M=20 |
| Mmpre_p1 g_nclamp_lvc1 g_pdpre_lvc1 drn_lvc1 drn_lvc1 pmos W=7 L=0.18 M=20 |
| Mmpre_n1 g_nclamp_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=3 |
| DD2 vddio vssd ddnw_sub_v5 area=10516.30 pj=468.870 m=1 |
| Mmncap src_bdy_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=8 M=15 |
| XXesd bdy2_b2b src_bdy_lvc1 vssd / s130_esd_gnd2gnd_120x2_lv_isosub |
| XPAD0 g_pad pad_bond w=60 l=70 m=1 |
| DD0 vddio src_bdy_lvc2 dipw_dnw_v5 area=4115.420 pj=264.630 m=1 |
| DD1 vddio src_bdy_lvc1 dipw_dnw_v5 area=5703.290 pj=340.890 m=1 |
| MmI58 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=8 M=6 |
| MmI59 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=8 M=10 |
| MmI60 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=4 M=1 |
| MmI43 g_nclamp_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=2 |
| RrI13 g_pad g_core 600.0u $[rm3] $W=23.945 $L=0.3 M=1 |
| MmI42 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=152 |
| RRM0 g_pad g_core 600.0u $[rm3] $W=24 $L=0.3 M=1 |
| Rrrc_res $PINS MINUS=g_pdpre_lvc1 PLUS=drn_lvc1 model=rpoly w=0.33 l=1953.3 |
| + m=1 segments=1 rType=Series |
| RrI46 $PINS MINUS=g_pdpre_lvc2 PLUS=net_78 model=rpoly w=0.33 l=203.96 m=1 |
| + segments=1 rType=Series |
| RrI45 $PINS MINUS=net_78 PLUS=net157 model=rpoly w=0.33 l=723.63 m=1 |
| + segments=1 rType=Series |
| RrI47 $PINS MINUS=net157 PLUS=net161 model=rpoly w=0.33 l=301.32 m=1 |
| + segments=1 rType=Series |
| MmI62 drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=5 L=0.18 M=20 |
| MmI61 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=0.18 M=38 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_hvclamp_wopad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_hvclamp_wopad drn_hvc ogc_hvc src_bdy_hvc |
| *.PININFO drn_hvc:B ogc_hvc:B src_bdy_hvc:B |
| Mmpre_p1 g_nclamp g_pdpre drn_hvc drn_hvc pmos_v5 W=7 L=0.5 M=50 |
| Mmnc1 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=8 M=15 |
| Mmpre_n1 g_nclamp g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=7 L=0.5 M=15 |
| Mmnc2 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=4 M=5 |
| DD0 ogc_hvc src_bdy_hvc dipw_dnw_v5 area=9511.980 pj=654.990 m=1 |
| Rrrc_res $PINS MINUS=g_pdpre PLUS=net014 model=rpoly w=0.33 l=470.66 m=1 |
| + segments=1 rType=Series |
| Mmclamp_xtor drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=20 L=0.5 M=120 |
| RrI37 $PINS MINUS=net014 PLUS=net013 model=rpoly w=0.33 l=1552.97 m=1 |
| + segments=1 rType=Series |
| DD1 ogc_hvc src_bdy_hvc ddnw_sub_v5 area=10370.10 pj=620.130 m=1 |
| RrI38 $PINS MINUS=net013 PLUS=drn_hvc model=rpoly w=0.33 l=703.63 m=1 |
| + segments=1 rType=Series |
| Mmcxtor2 drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=10 L=0.5 M=22 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_lvc_b2b_wopad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_lvc_b2b_wopad bdy2_b2b drn_lvc1 drn_lvc2 ogc_lvc |
| + src_bdy_lvc1 src_bdy_lvc2 vssd |
| *.PININFO bdy2_b2b:B drn_lvc1:B drn_lvc2:B ogc_lvc:B src_bdy_lvc1:B |
| *.PININFO src_bdy_lvc2:B vssd:B |
| RrI47 $PINS MINUS=net60 PLUS=net66 model=rpoly w=0.33 l=301.32 m=1 segments=1 |
| + rType=Series |
| MmI62 drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=5 L=0.18 M=20 |
| Mmpre_p1 g_nclamp_lvc1 g_pdpre_lvc1 drn_lvc1 drn_lvc1 pmos W=7 L=0.18 M=20 |
| MmI40 g_nclamp_lvc2 g_pdpre_lvc2 drn_lvc2 drn_lvc2 pmos W=7 L=0.18 M=20 |
| MmI43 g_nclamp_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=2 |
| MmI58 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=8 M=6 |
| MmI59 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=8 M=10 |
| MmI60 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=4 M=1 |
| Mmncap src_bdy_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=8 M=15 |
| Mmpre_n1 g_nclamp_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=3 |
| RrI44 $PINS MINUS=net66 PLUS=drn_lvc2 model=rpoly w=0.33 l=901.32 m=1 |
| + segments=1 rType=Series |
| XXesd bdy2_b2b src_bdy_lvc1 vssd / s130_esd_gnd2gnd_120x2_lv_isosub |
| RrI45 $PINS MINUS=net064 PLUS=net60 model=rpoly w=0.33 l=723.63 m=1 segments=1 |
| + rType=Series |
| DD1 ogc_lvc src_bdy_lvc1 dipw_dnw_v5 area=5703.290 pj=340.890 m=1 |
| DD2 ogc_lvc src_bdy_lvc2 dipw_dnw_v5 area=4115.420 pj=264.630 m=1 |
| RrI46 $PINS MINUS=net064 PLUS=g_pdpre_lvc2 model=rpoly w=0.33 l=203.96 m=1 |
| + segments=1 rType=Series |
| MmI42 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=152 |
| Rrrc_res $PINS MINUS=g_pdpre_lvc1 PLUS=drn_lvc1 model=rpoly w=0.33 l=1953.3 |
| + m=1 segments=1 rType=Series |
| DD0 ogc_lvc vssd ddnw_sub_v5 area=10516.30 pj=468.870 m=1 |
| Mmclamp_xtor drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=166 |
| MmI61 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=0.18 M=38 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_lvclamp |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_lvclamp drn_lvc ogc_lvc src_bdy_lvc |
| *.PININFO drn_lvc:B ogc_lvc:B src_bdy_lvc:B |
| DD1 ogc_lvc src_bdy_lvc ddnw_sub_v5 area=5939.680 pj=428.960 m=1 |
| Mmncap src_bdy_lvc g_pdpre_lvc1 src_bdy_lvc src_bdy_lvc nmos W=7 L=8 M=6 |
| MmI57 src_bdy_lvc g_pdpre_lvc1 src_bdy_lvc src_bdy_lvc nmos W=7 L=4 M=5 |
| Mmpre_n1 g_nclamp_lvc1 g_pdpre_lvc1 src_bdy_lvc src_bdy_lvc nmos W=7 L=0.18 M=2 |
| Mmclamp_xtor drn_lvc g_nclamp_lvc1 src_bdy_lvc src_bdy_lvc nmos W=7 L=0.18 |
| + M=204 |
| Mmpre_p1 g_nclamp_lvc1 g_pdpre_lvc1 drn_lvc drn_lvc pmos W=7 L=0.18 M=20 |
| DD0 ogc_lvc src_bdy_lvc dipw_dnw_v5 area=5327.440 pj=469.990 m=1 |
| Rrrc_res $PINS MINUS=drn_lvc PLUS=g_pdpre_lvc1 model=rpoly w=0.33 l=1952.97 |
| + m=1 segments=1 rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_power_hvc_wpad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_power_hvc_wpad amuxbus_a amuxbus_b drn_hvc ogc_hvc p_core |
| + p_pad src_bdy_hvc vccd vcchib vdda vddio vddio_q vssa vssd vssio vssio_q |
| + vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B drn_hvc:B ogc_hvc:B p_core:B p_pad:B |
| *.PININFO src_bdy_hvc:B vccd:B vcchib:B vdda:B vddio:B vddio_q:B vssa:B vssd:B |
| *.PININFO vssio:B vssio_q:B vswitch:B |
| Mmpre_p1 g_nclamp g_pdpre drn_hvc drn_hvc pmos_v5 W=7 L=0.5 M=50 |
| Mmnc1 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=8 M=15 |
| Mmpre_n1 g_nclamp g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=7 L=0.5 M=15 |
| Mmnc2 src_bdy_hvc g_pdpre src_bdy_hvc src_bdy_hvc nmos_v5 W=5 L=4 M=5 |
| XPAD0 p_pad pad_bond w=60 l=70 m=1 |
| RrI37 $PINS MINUS=net32 PLUS=net026 model=rpoly w=0.33 l=1552.97 m=1 |
| + segments=1 rType=Series |
| Rrrc_res $PINS MINUS=g_pdpre PLUS=net32 model=rpoly w=0.33 l=470.66 m=1 |
| + segments=1 rType=Series |
| Mmclamp_xtor drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=20 L=0.5 M=120 |
| RrI13 p_pad p_core 600.0u $[rm3] $W=23.9 $L=0.3 M=2 |
| Mmcxtor2 drn_hvc g_nclamp src_bdy_hvc src_bdy_hvc nmos_v5 W=10 L=0.5 M=22 |
| DD0 vddio vssd ddnw_sub_v5 area=10358.70 pj=619.080 m=1 |
| DD1 vddio src_bdy_hvc dipw_dnw_v5 area=9495.080 pj=653.940 m=1 |
| RrI38 $PINS MINUS=net026 PLUS=drn_hvc model=rpoly w=0.33 l=703.63 m=1 |
| + segments=1 rType=Series |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_power_lvc_wpad |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_power_lvc_wpad amuxbus_a amuxbus_b bdy2_b2b drn_lvc1 |
| + drn_lvc2 ogc_lvc p_core p_pad src_bdy_lvc1 src_bdy_lvc2 vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B bdy2_b2b:B drn_lvc1:B drn_lvc2:B ogc_lvc:B |
| *.PININFO p_core:B p_pad:B src_bdy_lvc1:B src_bdy_lvc2:B vccd:B vcchib:B |
| *.PININFO vdda:B vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| RrI44 $PINS MINUS=net161 PLUS=drn_lvc2 model=rpoly w=0.33 l=901.32 m=1 |
| + segments=1 rType=Series |
| Mmclamp_xtor drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=166 |
| MmI40 g_nclamp_lvc2 g_pdpre_lvc2 drn_lvc2 drn_lvc2 pmos W=7 L=0.18 M=20 |
| Mmpre_p1 g_nclamp_lvc1 g_pdpre_lvc1 drn_lvc1 drn_lvc1 pmos W=7 L=0.18 M=20 |
| Mmpre_n1 g_nclamp_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=0.18 |
| + M=3 |
| DD2 vddio vssd ddnw_sub_v5 area=10516.30 pj=468.870 m=1 |
| Mmncap src_bdy_lvc1 g_pdpre_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=7 L=8 M=15 |
| XXesd bdy2_b2b src_bdy_lvc1 vssd / s130_esd_gnd2gnd_120x2_lv_isosub |
| XPAD0 p_pad pad_bond w=60 l=70 m=1 |
| DD0 vddio src_bdy_lvc2 dipw_dnw_v5 area=4115.420 pj=264.630 m=1 |
| DD1 vddio src_bdy_lvc1 dipw_dnw_v5 area=5703.290 pj=340.890 m=1 |
| MmI58 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=8 M=6 |
| MmI59 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=8 M=10 |
| MmI60 src_bdy_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=4 M=1 |
| MmI43 g_nclamp_lvc2 g_pdpre_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=2 |
| RrI13 p_pad p_core 600.0u $[rm3] $W=23.945 $L=0.3 M=1 |
| MmI42 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=7 L=0.18 M=152 |
| RRM0 p_pad p_core 600.0u $[rm3] $W=24 $L=0.3 M=1 |
| Rrrc_res $PINS MINUS=g_pdpre_lvc1 PLUS=drn_lvc1 model=rpoly w=0.33 l=1953.3 |
| + m=1 segments=1 rType=Series |
| RrI46 $PINS MINUS=g_pdpre_lvc2 PLUS=net_78 model=rpoly w=0.33 l=203.96 m=1 |
| + segments=1 rType=Series |
| RrI45 $PINS MINUS=net_78 PLUS=net157 model=rpoly w=0.33 l=723.63 m=1 |
| + segments=1 rType=Series |
| RrI47 $PINS MINUS=net157 PLUS=net161 model=rpoly w=0.33 l=301.32 m=1 |
| + segments=1 rType=Series |
| MmI62 drn_lvc1 g_nclamp_lvc1 src_bdy_lvc1 src_bdy_lvc1 nmos W=5 L=0.18 M=20 |
| MmI61 drn_lvc2 g_nclamp_lvc2 src_bdy_lvc2 src_bdy_lvc2 nmos W=5 L=0.18 M=38 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_pwrdet_lshv2hv_0 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_pwrdet_lshv2hv_0 in out pd_hv vgnd vpwrin vpwrout |
| *.PININFO in:I pd_hv:I out:O vgnd:B vpwrin:B vpwrout:B |
| MmI28 Ab in vgnd vgnd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI16 net_089 cross2 vgnd vgnd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI11 net120 cross1 vgnd vgnd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI6 pd_hvb pd_hv vgnd vgnd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI8 Abb Ab vgnd vgnd nmos_v5 W=0.75 L=0.5 M=1 |
| MmI2 cross1 cross2 vgnd vgnd nmos_v5 W=0.42 L=1 M=1 |
| MmI1 cross2 cross1 vgnd vgnd nmos_v5 W=0.42 L=1 M=1 |
| MmI29 cross1 pd_hv vgnd vgnd nmos_v5 W=1 L=0.8 M=1 |
| MmI19 cross1 cross2 vpwrout vpwrout pmos_v5 W=0.42 L=1 M=1 |
| MmI18 cross2 cross1 vpwrout vpwrout pmos_v5 W=0.42 L=1 M=1 |
| MmI30 pd_hvb pd_hv vpwrout vpwrout pmos_v5 W=1.5 L=0.5 M=1 |
| MmI15 net_089 cross2 vpwrout vpwrout pmos_v5 W=1.5 L=0.5 M=2 |
| MmI5 net120 cross1 vpwrout vpwrout pmos_v5 W=3 L=0.5 M=1 |
| MmI12 vgnd vgnd vgnd vgnd nmos_v5 W=1.5 L=0.5 M=3 |
| MmI13 vpwrout vpwrout vpwrout vpwrout pmos_v5 W=3 L=0.5 M=2 |
| MmI3 net_158 pd_hvb vgnd vgnd nmos_v5 W=3 L=0.5 M=1 |
| MmI32 net_130 pd_hvb vgnd vgnd nmos_v5 W=3 L=0.5 M=1 |
| MmI22 cross1 Ab net_158 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI21 cross2 Abb net_130 vgnd nmos_v5 W=3 L=0.5 M=3 |
| MmI10 out net120 vgnd vgnd nmos_v5 W=1.5 L=0.5 M=4 |
| MmI4 out net120 vpwrout vpwrout pmos_v5 W=3 L=0.5 M=8 |
| MmI7 Abb Ab vpwrin vpwrin pmos_v5 W=0.75 L=0.5 M=1 |
| MmI27 Ab in vpwrin vpwrin pmos_v5 W=0.75 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_pwrdet_inv_4 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_pwrdet_inv_4 A Y vgnd vnb vpb vpwr |
| *.PININFO A:I vgnd:I vnb:I vpb:I vpwr:I Y:O |
| MmMIP1 Y A vpwr vpb pmos_v5 W=1.5 L=0.5 M=4 |
| MmMIN1 Y A vgnd vnb nmos_v5 W=0.75 L=0.5 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_pwrdet_buf_4 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_pwrdet_buf_4 A X vgnd vnb vpb vpwr |
| *.PININFO A:I vgnd:I vnb:I vpb:I vpwr:I X:O |
| MmMIN1 Ab A vgnd vnb nmos_v5 W=0.75 L=0.5 M=1 |
| MmMIN2 X Ab vgnd vnb nmos_v5 W=0.75 L=0.5 M=4 |
| MmMIP1 Ab A vpwr vpb pmos_v5 W=1.5 L=0.5 M=1 |
| MmMIP2 X Ab vpwr vpb pmos_v5 W=1.5 L=0.5 M=4 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_pwrdet_vddd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_pwrdet_vddd out vddd vddio_q vssa vssd |
| *.PININFO vddd:I vddio_q:I vssa:I out:O vssd:B |
| MmI295 net194 n2 vddio_q vddio_q pmos_v5 W=1 L=4 M=2 |
| MmI288 n2 n1 vssa vssa nmos_v5 W=7 L=0.5 M=1 |
| MmI294 net194 n2 vssa vssa nmos_v5 W=1 L=4 M=1 |
| MmI24 vssa n2 vssa vssa nmos_nat_v5 W=10 L=2 M=5 |
| DD0 vddio_q vssa dipw_dnw_v5 area=242.7910 pj=63.140 m=1 |
| MmI20 vddio_q vddio_q vddio_q vddio_q pmos_v5 W=1.5 L=0.5 M=1 |
| MmI19 vddio_q vddio_q vddio_q vddio_q pmos_v5 W=1.5 L=0.5 M=1 |
| RrI2 $PINS B=vssd MINUS=net132 PLUS=p0 model=rndiff_v5 w=0.3 l=3153.89 m=1 |
| + segments=1 rType=Parallel |
| MmI13 vssa net129 vssa vssa nmos_nat_v5 W=10 L=2 M=15 |
| MmI18 vssa vssa vssa vssa nmos_v5 W=3 L=0.5 M=1 |
| MmI16 vssa vssa vssa vssa nmos_v5 W=1 L=4 M=2 |
| MmI17 vssa vssa vssa vssa nmos_v5 W=1 L=0.5 M=2 |
| MmI21 vssa vssa vssa vssa nmos_v5 W=0.75 L=0.5 M=1 |
| MmI22 vssa vssa vssa vssa nmos_v5 W=0.75 L=0.5 M=1 |
| MmI15 vssa vssa vssa vssa nmos_v5 W=1 L=8 M=1 |
| MmI297 out net194 vddio_q vddio_q pmos_v5 W=1 L=2 M=2 |
| MmI284 n2 n1 net117 vddio_q pmos_v5 W=1 L=8 M=1 |
| MmI10 net117 n1 vddio_q vddio_q pmos_v5 W=1 L=8 M=1 |
| MmI296 out net194 vssa vssa nmos_v5 W=1 L=2 M=1 |
| RrI3 $PINS B=vssd MINUS=vddio_q PLUS=net138 model=rndiff_v5 w=0.3 l=1341.12 |
| + m=1 segments=1 rType=Parallel |
| XXI0 net055 vddd / s130_esd_res250only_small |
| MmI285 n1 net129 p0 vddio_q pmos_v5 W=7 L=0.5 M=4 |
| RrI11 $PINS B=vssd MINUS=net055 PLUS=net129 model=rndiff_v5 w=0.3 l=69.74 m=1 |
| + segments=1 rType=Parallel |
| RrI12 $PINS B=vssd MINUS=vddd PLUS=vddd model=rndiff_v5 w=0.3 l=69.74 m=1 |
| + segments=1 rType=Parallel |
| DD1 vddio_q vssd ddnw_sub_v5 area=719.0140 pj=112.450 m=1 |
| RrI299 $PINS MINUS=vssa PLUS=vssa model=rpoly w=0.33 l=15.635 m=1 segments=1 |
| + rType=Parallel |
| MmI291 net182 net129 net178 vssa nmos_v5 W=3 L=8 M=1 |
| MmI289 n1 net129 net182 vssa nmos_v5 W=3 L=8 M=1 |
| MmI292 net178 net129 vssa vssa nmos_v5 W=3 L=8 M=1 |
| RrI9 $PINS MINUS=net132 PLUS=net138 model=rpoly w=0.33 l=1952.97 m=1 |
| + segments=1 rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_pwrdet_vddio |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_pwrdet_vddio out rst_por_hv_n vccd vddd vddio_q vssa vssd |
| *.PININFO rst_por_hv_n:I vccd:I vddd:I vddio_q:I vssa:I out:O vssd:B |
| MmI16 net_1 out_1 vssa vssa nmos_v5 W=1 L=8 M=1 |
| MmI15 net_1 out_1 vddd vddd pmos_v5 W=1 L=8 M=2 |
| XXI7 net_1 out vssa vssa vddd vddd / s130iom0_pwrdet_inv_4 |
| MmI21 pre_out out_1 net126 vssa nmos_v5 W=1.5 L=4 M=2 |
| MmI22 net126 rst_por_hv_n vssa vssa nmos_v5 W=1.5 L=4 M=2 |
| MmI17 out_1 pre_out vssa vssa nmos_v5 W=1.5 L=4 M=2 |
| DD0 vddd vssd ddnw_sub_v5 area=1905.730 pj=250.020 m=1 |
| MmI19 pre_out out_1 vddd vddd pmos_v5 W=0.42 L=20 M=1 |
| MmI14 out_1 pre_out vddd vddd pmos_v5 W=0.42 L=20 M=1 |
| MmI1 out_1 vddio_b vssa vssa nmos_v5 W=5 L=0.5 M=4 |
| MmI0 pre_out vddio_r vssa vssa nmos_v5 W=5 L=0.5 M=4 |
| MmI24 vssa vddio_r vssa vssa nmos_nat_v5 W=10 L=2 M=20 |
| MmI27 vssa vssa vssa vssa nmos_v5 W=0.75 L=0.5 M=1 |
| MmI26 vssa vssa vssa vssa nmos_v5 W=0.75 L=0.5 M=1 |
| MmI18 vddio_b vddio_r vccd vccd pmos_v5 W=7 L=0.5 M=8 |
| MmI6 vddd vddd vddd vddd pmos_v5 W=1.5 L=0.5 M=1 |
| MmI3 vddd vddd vddd vddd pmos_v5 W=1.5 L=0.5 M=1 |
| XXI2 net056 vddio_q / s130_esd_res250only_small |
| MmI20 pre_out rst_por_hv_n vddd vddd pmos_v5 W=1 L=1 M=1 |
| MmI12 net118 vddio_r net106 vssa nmos_v5 W=3 L=8 M=1 |
| MmI11 vddio_b vddio_r net118 vssa nmos_v5 W=3 L=8 M=1 |
| MmI13 net106 vddio_r vssa vssa nmos_v5 W=3 L=8 M=1 |
| DD1 vddd vssa dipw_dnw_v5 area=1656.690 pj=233.540 m=1 |
| RrI25 $PINS B=vssd MINUS=net056 PLUS=vddio_r model=rndiff_v5 w=0.3 l=279.49 |
| + m=1 segments=1 rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_pwrdetv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_pwrdetv2 in1_vddd_hv in1_vddio_hv in2_vddd_hv |
| + in2_vddio_hv in3_vddd_hv in3_vddio_hv out1_vddd_hv out1_vddio_hv |
| + out2_vddd_hv out2_vddio_hv out3_vddd_hv out3_vddio_hv rst_por_hv_n |
| + tie_lo_esd vccd vddd1 vddd2 vddd_present_vddio_hv vddio_present_vddd_hv |
| + vddio_q vssa vssd vssio_q |
| *.PININFO in1_vddd_hv:I in1_vddio_hv:I in2_vddd_hv:I in2_vddio_hv:I |
| *.PININFO in3_vddd_hv:I in3_vddio_hv:I rst_por_hv_n:I out1_vddd_hv:O |
| *.PININFO out1_vddio_hv:O out2_vddd_hv:O out2_vddio_hv:O out3_vddd_hv:O |
| *.PININFO out3_vddio_hv:O tie_lo_esd:O vddd_present_vddio_hv:O |
| *.PININFO vddio_present_vddd_hv:O vccd:B vddd1:B vddd2:B vddio_q:B vssa:B |
| *.PININFO vssd:B vssio_q:B |
| XXI3 in1_vddio_hv out1_vddd_hv net174 vssd vddio_q vddd1 / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI4 in2_vddio_hv out2_vddd_hv net174 vssd vddio_q vddd1 / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI5 in3_vddio_hv out3_vddd_hv net174 vssd vddio_q vddd1 / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI17 in1_vddd_hv out1_vddio_hv net160 vssd vddd2 vddio_q / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI16 in2_vddd_hv out2_vddio_hv net160 vssd vddd2 vddio_q / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI15 in3_vddd_hv out3_vddio_hv net160 vssd vddd2 vddio_q / |
| + s130iom0_pwrdet_lshv2hv_0 |
| XXI7 net166 net174 vssd vssd vddd1 vddd1 / s130iom0_pwrdet_inv_4 |
| XXI19 net178 net160 vssd vssd vddio_q vddio_q / s130iom0_pwrdet_inv_4 |
| XXI2 net166 vddio_present_vddd_hv vssd vssd vddd1 vddd1 / s130iom0_pwrdet_buf_4 |
| XXI18 net178 vddd_present_vddio_hv vssd vssd vddio_q vddio_q / |
| + s130iom0_pwrdet_buf_4 |
| XXI49 vssd tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| XXI0 net178 vddd2 vddio_q vssa vssd / s130iom0_pwrdet_vddd |
| XXI1 net166 rst_por_hv_n vccd vddd1 vddio_q vssa vssd / s130iom0_pwrdet_vddio |
| DD1 vddio_q vssd dipw_dnw_v5 area=349.2630 pj=76.010 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp1_res |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp1_res a b |
| *.PININFO a:B b:B |
| RRNP0_1_1 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_2 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_3 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_4 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_5 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_6 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_7 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_8 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_9 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=112 m=1 segments=9 |
| + rType=Series |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp1_div |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp1_div en_tp1 force_tp1 tp1 tp1_div vnb vssd |
| *.PININFO en_tp1:I force_tp1:I tp1:I vnb:I vssd:I tp1_div:O |
| XXRESLO tp1_div_int tp1_sw / s130iom0_tp1_res |
| XXRESHI<6> tp1 tp1_res<5> / s130iom0_tp1_res |
| XXRESHI<5> tp1_res<5> tp1_res<4> / s130iom0_tp1_res |
| XXRESHI<4> tp1_res<4> tp1_res<3> / s130iom0_tp1_res |
| XXRESHI<3> tp1_res<3> tp1_res<2> / s130iom0_tp1_res |
| XXRESHI<2> tp1_res<2> tp1_res<1> / s130iom0_tp1_res |
| XXRESHI<1> tp1_res<1> tp1_div_int / s130iom0_tp1_res |
| MmM0 tp1_sw en_tp1 vssd vnb nmos_v5 W=5 L=0.5 M=8 |
| MmM2 tp1_div_int en_tp1 tp1_div vnb nmos_v5 W=5 L=0.5 M=2 |
| MmM1 tp1_div_int force_tp1 vssd vnb nmos_v5 W=5 L=0.5 M=2 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_res250only |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_res250only pad rout |
| *.PININFO pad:B rout:B |
| RrI228 $PINS MINUS=rout PLUS=pad model=rpoly w=4 l=20.19 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130_esd |
| * Cell Name: s130_esd_signal_40_sym_hv_2k_dnwl_aup1_b |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130_esd_signal_40_sym_hv_2k_dnwl_aup1_b body g<5> g<4> g<3> g<2> g<1> |
| + g<0> gate<9> gate<8> gate<7> gate<6> gate<5> gate<4> gate<3> gate<2> gate<1> |
| + gate<0> nwellRing pad<4> pad<3> pad<2> pad<1> pad<0> vssd |
| *.PININFO gate<9>:I gate<8>:I gate<7>:I gate<6>:I gate<5>:I gate<4>:I |
| *.PININFO gate<3>:I gate<2>:I gate<1>:I gate<0>:I nwellRing:I body:B g<5>:B |
| *.PININFO g<4>:B g<3>:B g<2>:B g<1>:B g<0>:B pad<4>:B pad<3>:B pad<2>:B |
| *.PININFO pad<1>:B pad<0>:B vssd:B |
| DD0 nwellRing vssd ddnw_sub_v5 area=3741.660 pj=250.50 m=1 |
| DD1 nwellRing body dipw_dnw_v5 area=3374.040 pj=238.550 m=1 |
| MmesdNfet0<1> pad<0> gate<1> g<1> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet0<0> pad<0> gate<0> g<0> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet1<1> pad<1> gate<3> g<2> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet1<0> pad<1> gate<2> g<1> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet3<1> pad<3> gate<7> g<4> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet3<0> pad<3> gate<6> g<3> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet2<1> pad<2> gate<5> g<3> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet2<0> pad<2> gate<4> g<2> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet4<1> pad<4> gate<9> g<5> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| MmesdNfet4<0> pad<4> gate<8> g<4> body nmos_esd_v5 W=40.31 L=0.55 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_tp1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_tp1 amuxbus_a amuxbus_b en_tp1 tp1 tp1_div tp1_out vccd |
| + vcchib vdda vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO en_tp1:I tp1_div:O amuxbus_a:B amuxbus_b:B tp1:B tp1_out:B vccd:B |
| *.PININFO vcchib:B vdda:B vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B |
| *.PININFO vswitch:B |
| XXTP1_DIV en_tp1 vssd tp1_out tp1_div vssd vssd / s130iom0_tp1_div |
| XI0 tp1 tp1_out / s130_esd_res250only |
| XXESD vssio vssio vssio vssio vssio vssio vssio net21 net21 net21 net21 net21 |
| + net21 net21 net21 net21 net21 vddio tp1 tp1 tp1 tp1 tp1 vssd / |
| + s130_esd_signal_40_sym_hv_2k_dnwl_aup1_b |
| XPAD0 tp1 pad_bond w=60 l=70 m=1 |
| RrI18 $PINS MINUS=net21 PLUS=vssio model=rpoly w=0.5 l=10.2 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp2_res |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp2_res a b |
| *.PININFO a:B b:B |
| RRNP0_1_1 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_2 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_3 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_4 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_5 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_6 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_7 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_8 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| RRNP0_1_9 $PINS MINUS=b PLUS=a model=rpoly w=0.4 l=87 m=1 segments=9 |
| + rType=Series |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp2_inv_1 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp2_inv_1 A Y vgnd vnb vpb vpwr |
| *.PININFO A:I vgnd:I vnb:I vpb:I vpwr:I Y:O |
| MmMIP1 Y A vpwr vpb pmos_v5 W=1.5 L=0.5 M=1 |
| MmMIN1 Y A vgnd vnb nmos_v5 W=0.75 L=0.5 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp2_ls |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp2_ls in out vgnd vhv |
| *.PININFO in:I vgnd:I vhv:I out:O |
| MmM5 outb out vhv vhv pmos_v5 W=1 L=0.6 M=1 |
| MmM4 out outb vhv vhv pmos_v5 W=1 L=0.6 M=1 |
| MmM1 ainv in vhv vhv pmos_v5 W=0.75 L=2 M=1 |
| MmM0 ainv in vgnd vgnd nmos_v5 W=5 L=0.8 M=2 |
| MmM2 out ainv vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| MmM3 outb in vgnd vgnd nmos_v5 W=3 L=0.6 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_tp2_div |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_tp2_div en_tp2 force_tp2 tp2 tp2_div vccd vio vssd |
| *.PININFO en_tp2:I force_tp2:I tp2:I vccd:I vio:I vssd:I tp2_div:O |
| XXRESLO<8> tp2 tp2_res<7> / s130iom0_tp2_res |
| XXRESLO<7> tp2_res<7> tp2_res<6> / s130iom0_tp2_res |
| XXRESLO<6> tp2_res<6> tp2_res<5> / s130iom0_tp2_res |
| XXRESLO<5> tp2_res<5> tp2_res<4> / s130iom0_tp2_res |
| XXRESLO<4> tp2_res<4> tp2_res<3> / s130iom0_tp2_res |
| XXRESLO<3> tp2_res<3> tp2_res<2> / s130iom0_tp2_res |
| XXRESLO<2> tp2_res<2> tp2_res<1> / s130iom0_tp2_res |
| XXRESLO<1> tp2_res<1> tp2_div_int / s130iom0_tp2_res |
| XXRESHI rtop tp2div / s130iom0_tp2_res |
| DD1 vio vssd ddnw_sub_v5 area=103.2570 pj=43.480 m=1 |
| MmM4 rtop enb_tp2 vccd vccd pmos_v5 W=5 L=0.5 M=8 |
| MmM1 tp2div enb_tp2 pullup pullup pmos_v5 W=5 L=0.6 M=4 |
| MmM2 tp2_div en_tp2_hv pullup vssd nmos_v5 W=3 L=0.6 M=2 |
| MmM6 en_tp2_hv enb_tp2 vssd vssd nmos_v5 W=1 L=1 M=1 |
| MmM3 pullup enb_tp2 vssd vssd nmos_v5 W=1 L=1 M=1 |
| XXU3 enb_tp2 en_tp2_buf vssd vssd vccd vccd / s130iom0_tp2_inv_1 |
| XXU2 en_tp2 enb_tp2 vssd vssd vccd vccd / s130iom0_tp2_inv_1 |
| XXU1 force_tp2 forceb_tp2 vssd vssd vccd vccd / s130iom0_tp2_inv_1 |
| MmM5 rtop forceb_tp2 vccd vccd pmos_v5 W=5 L=0.5 M=2 |
| XXLEVSHIFT en_tp2 en_tp2_hv vssd vio / s130iom0_tp2_ls |
| MmM0 tp2div en_tp2_buf tp2_div_int tp2div nmos_nat_v5 W=10 L=0.9 M=2 |
| DD0 vio tp2div dipw_dnw_v5 area=60.44280 pj=34.720 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_tp2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_tp2 amuxbus_a amuxbus_b en_tp2 tp2 tp2_div tp2_out vccd |
| + vcchib vdda vddio vddio_q vneg vssa vssd vssio vssio_q vswitch |
| *.PININFO en_tp2:I tp2_div:O amuxbus_a:B amuxbus_b:B tp2:B tp2_out:B vccd:B |
| *.PININFO vcchib:B vdda:B vddio:B vddio_q:B vneg:B vssa:B vssd:B vssio:B |
| *.PININFO vssio_q:B vswitch:B |
| XXRESD tp2 tp2_out / s130_esd_res250only |
| XXTP2_DIV en_tp2 vssd tp2_out tp2_div vccd vddio vssd / s130iom0_tp2_div |
| XXESD vneg vssio vssio vssio vssio vssio vssio net73 net73 net73 net73 net73 |
| + net73 net73 net73 net73 net73 vddio tp2 tp2 tp2 tp2 tp2 vssd / |
| + s130_esd_signal_40_sym_hv_2k_dnwl_aup1_b |
| XPAD0 tp2 pad_bond w=60 l=70 m=1 |
| RrI18 $PINS MINUS=net73 PLUS=vneg model=rpoly w=0.5 l=10.2 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_tp3 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_tp3 tp3 tp3_out vddd vssd |
| *.PININFO tp3:B tp3_out:B vddd:B vssd:B |
| XXRESD tp3 tp3_out / s130_esd_res250only |
| XXESD vssd vssd vssd vssd vssd vssd vssd net22 net22 net22 net22 net22 net22 |
| + net22 net22 net22 net22 vddd tp3 tp3 tp3 tp3 tp3 vssd / |
| + s130_esd_signal_40_sym_hv_2k_dnwl_aup1_b |
| XPAD0 tp3 pad_bond w=70 l=70 m=1 |
| RrR1 $PINS MINUS=net22 PLUS=vssd model=rpoly w=0.5 l=10.2 m=1 segments=1 |
| + rType=Parallel |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_vrefcapv2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_vrefcapv2 amuxbus_a amuxbus_b cneg cpos vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO amuxbus_a:B amuxbus_b:B cneg:B cpos:B vccd:B vcchib:B vdda:B vddio:B |
| *.PININFO vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| DD0 vddio_q cneg dipw_dnw_v5 area=2842.760 pj=423.120 m=1 |
| DD1 vddio_q vssd ddnw_sub_v5 area=3282.820 pj=431.360 m=1 |
| MmI334 cneg cpos cneg cneg nmos_nat_v5 W=10 L=0.9 M=180 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_wpu |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_wpu pad vddio vssd |
| *.PININFO pad:B vddio:B vssd:B |
| XXesdr pad net15 / s130_esd_res250only_small |
| XX5kres vddio net15 vssd / s130iom0_com_res_weak |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_inv_hys |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_inv_hys in_h out_h vcc_io vssd |
| *.PININFO in_h:I vcc_io:I vssd:I out_h:O |
| MmI9 out_h out_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI8 out_h_n in_h pmid1 vcc_io pmos_v5 W=3 L=1 M=1 |
| MmI7 pmid1 in_h vcc_io vcc_io pmos_v5 W=3 L=1 M=1 |
| MmI10 pmid1 out_h vcc_io vcc_io pmos_v5 W=0.42 L=1 M=1 |
| MmI6 out_h out_h_n vssd vssd nmos_v5 W=1 L=0.5 M=1 |
| MmI11 nmid1 out_h vssd vssd nmos_v5 W=0.42 L=1 M=1 |
| MmI4 out_h_n in_h nmid1 vssd nmos_v5 W=1 L=1 M=1 |
| MmI5 nmid1 in_h vssd vssd nmos_v5 W=1 L=1 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_rcfilter_lpf |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_rcfilter_lpf in out vcc_io vssd |
| *.PININFO in:I out:O vcc_io:B vssd:B |
| RRM7 net12 vssd 4.3m $[rm1] $W=0.29 $L=0.01 M=1 |
| RRM6 net16 vssd 4.3m $[rm1] $W=0.29 $L=0.01 M=1 |
| RRM5 net19 vssd 4.3m $[rm1] $W=0.29 $L=0.01 M=1 |
| RRM4 net23 vssd 4.3m $[rm1] $W=0.29 $L=0.01 M=1 |
| XXI196 net12 net27 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI179 net11 net15 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI174 net9 net11 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI172 in net5 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI184 net19 net18 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI185 net23 net20 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI195 net16 net13 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI178 net15 net17 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI177 net34 net22 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI176 net38 net24 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI175 net7 net9 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| XXI173 net5 net7 vssd vssd vcc_io / s130iom0_xres_rcfilter_lpf_rcunit |
| RRM3 net24 out 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM1 net17 net34 4.8m $[rm1] $W=0.26 $L=0.01 M=1 |
| RRM2 net22 net38 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| RRM0 net9 net11 1.9m $[rm1] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_in_buf |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_in_buf en_h in_h in_vt out_h out_h_n vcc_io vgnd vpwr |
| + vtrip_sel_h_n |
| *.PININFO en_h:I in_h:I in_vt:I vcc_io:I vgnd:I vpwr:I vtrip_sel_h_n:I out_h:O |
| *.PININFO out_h_n:O |
| MmI574 net118 out_a net137 vgnd nmos_v5 W=3 L=1 M=2 |
| MmI571 net118 out_a vcc_io vgnd nmos_v5 W=1 L=1 M=1 |
| MmI598 net118 out_a vcc_io vgnd nmos_v5 W=0.42 L=1 M=1 |
| Mmpd1 net118 in_h net117 vgnd nmos_v5 W=5 L=1 M=2 |
| MmI597 net118 out_a net137 vgnd nmos_v5 W=0.75 L=1 M=1 |
| MmI570 out_a in_h net118 vgnd nmos_v5 W=5 L=0.5 M=3 |
| Mmpd_hrng net118 in_vt net117 vgnd nmos_v5 W=3 L=1 M=12 |
| MmI592 out_h out_h_n vgnd vgnd nmos_v5 W=1 L=0.5 M=3 |
| Mmpu2 net2 out_a vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI593 out_h out_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=3 |
| Mmpd2 net2 out_a vgnd vgnd nmos_v5 W=1 L=0.5 M=2 |
| MmI589 out_h_n net2 vgnd vgnd nmos_v5 W=1 L=0.5 M=2 |
| MmI577 out_a vtrip_sel_h net4 vcc_io pmos_v5 W=3 L=0.5 M=2 |
| Mmpuen_2 out_a en_h vcc_io vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI590 out_h_n net2 vcc_io vcc_io pmos_v5 W=3 L=0.5 M=2 |
| Mmpden_1 net117 en_h vgnd vgnd nmos_v5 W=3 L=0.6 M=12 |
| MmI584 net103 net103 net115 vgnd nmos_nat_v5 W=1 L=0.9 M=1 |
| MmI585 net115 net115 out_a vgnd nmos_nat_v5 W=1 L=0.9 M=1 |
| Mmpu1_midopt net3 in_h vcc_io vcc_io pmos_v5 W=5 L=0.8 M=2 |
| Mmpu1 net3 in_h vcc_io vcc_io pmos_v5 W=7 L=0.8 M=3 |
| MmI575 vcc_io vtrip_sel_h net137 vcc_io pmos_v5 W=0.75 L=0.5 M=2 |
| Mmpu1_mid_nat net4 vpwr net103 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| MmI567 net4 in_h net3 vcc_io pmos_v5 W=5 L=0.5 M=2 |
| MmI568 vgnd out_a net3 vcc_io pmos_v5 W=0.75 L=2 M=1 |
| MmI578 out_a in_h net153 vcc_io pmos_v5 W=5 L=0.5 M=4 |
| MmI579 net153 in_h vcc_io vcc_io pmos_v5 W=7 L=0.8 M=1 |
| XXI576 vtrip_sel_h_n vtrip_sel_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| MmI582 vgnd out_a net153 vcc_io pmos_v5 W=5 L=1 M=1 |
| Mmdis_trip_sel1 in_vt vtrip_sel_h_n vgnd vgnd nmos_v5 W=3 L=1 M=1 |
| RRM0 net115 out_a 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| MmI595 net077 in_vt net117 vgnd nmos_v5 W=3 L=1 M=8 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_ipath |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_ipath in_h in_vt out out_h vcchib vddio_q vssd |
| *.PININFO in_h:I in_vt:I out:O out_h:O vcchib:B vddio_q:B vssd:B |
| XXhv_drv1 out_hysbuf_h out_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| XXhyst_buf out_rcfilt_h out_hysbuf_h vddio_q vssd / s130iom0_xres_inv_hys |
| XXrcfilt out_gpio_h out_rcfilt_h vddio_q vssd / s130iom0_xres_rcfilter_lpf |
| XXhv_drv2 out_h_n out_h vssd vddio_q / s130iom0_hvsbt_inv_x4 |
| XXhv_lv_ls out_hysbuf_h net56 out vcchib vddio_q vssd / s130iom0_xres_hvlv_ls |
| XXgpio_inbuf vddio_q in_h in_vt out_gpio_h net40 vddio_q vssd vcchib vddio_q / |
| + s130iom0_gpio_in_buf |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pddrvr_strong |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pddrvr_strong force_lo_h force_lovol_h pad pd_h<3> |
| + pd_h<2> tie_lo_esd vcc_io vgnd_io vssd vssio_amx |
| *.PININFO force_lo_h:I force_lovol_h:I pd_h<3>:I pd_h<2>:I vcc_io:I vgnd_io:I |
| *.PININFO vssio_amx:I tie_lo_esd:O pad:B vssd:B |
| XXn11<2> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<1> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<0> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<2> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<1> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<0> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<2> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<1> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<0> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<2> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<1> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<0> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn12 pad net070 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<2> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<1> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<0> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<3> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<2> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<1> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<0> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn13 pad net078 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn31 pad net080 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXI49 vgnd_io tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| DD1 vcc_io vgnd_io dipw_dnw_v5 area=1576.750 pj=188.140 m=1 |
| DD0 vcc_io vssd ddnw_sub_v5 area=1791.380 pj=197.770 m=1 |
| RRM0 net070 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net078 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM3 net016 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM5 net057 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM6 net022 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM7 net076 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net068 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM4 net080 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_buf_localesd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_buf_localesd in_h out_h out_vt vcc_io vgnd vtrip_sel_h |
| *.PININFO in_h:I vtrip_sel_h:I out_h:O out_vt:O vcc_io:B vgnd:B |
| XXggnfet2 vgnd out_vt vgnd vcc_io vgnd / s130_esd_signal_5_sym_hv_local_5term |
| XXggnfet5 vgnd vcc_io vgnd vcc_io out_vt / s130_esd_signal_5_sym_hv_local_5term |
| XXggnfet6 vgnd vcc_io vgnd vcc_io out_h / s130_esd_signal_5_sym_hv_local_5term |
| XXggnfet1 vgnd out_h vgnd vcc_io vgnd / s130_esd_signal_5_sym_hv_local_5term |
| XXesd_res in_h out_h / s130_esd_res250only_small |
| Mmhv_passgate out_h vtrip_sel_h out_vt vgnd nmos_v5 W=3 L=1 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_esd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_esd out_h out_vt pad vddio vssd vssio |
| *.PININFO out_h:B out_vt:B pad:B vddio:B vssd:B vssio:B |
| XXpddrvr_strong tie_lo_esd tie_lo_esd pad tie_lo_esd tie_lo_esd tie_lo_esd |
| + vddio vssio vssd vssio / s130iom0_gpio_pddrvr_strong |
| XXpudrvr_strong pad tie_hi_esd tie_hi_esd tie_hi_esd vddio vssd / |
| + s130iom0_gpio_pudrvr_strong |
| XXesd pad out_h out_vt vddio vssd vssd / s130iom0_gpio_buf_localesd |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_xres |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_xres amuxbus_a amuxbus_b out out_h pad vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO out:O out_h:O amuxbus_a:B amuxbus_b:B pad:B vccd:B vcchib:B vdda:B |
| *.PININFO vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| XXweakpullup pad vddio vssd / s130iom0_xres_wpu |
| XXibuf in_h in_vt out out_h vcchib vddio_q vssd / s130iom0_xres_ipath |
| XXxresesd in_h in_vt pad vddio vssd vssio / s130iom0_xres_esd |
| XPAD0 pad pad_bond w=60 l=70 m=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pddrvr_strong_xres_2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pddrvr_strong_xres_2 force_lo_h force_lovol_h pad |
| + pd_h<3> pd_h<2> tie_lo_esd vcc_io vgnd_io vssd vssio_amx |
| *.PININFO force_lo_h:I force_lovol_h:I pd_h<3>:I pd_h<2>:I vcc_io:I vgnd_io:I |
| *.PININFO vssio_amx:I tie_lo_esd:O pad:B vssd:B |
| XXn11<2> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<1> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<0> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<2> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<1> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<0> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<2> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<1> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<0> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<2> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<1> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<0> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn12 pad net070 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<2> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<1> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<0> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<3> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<2> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<1> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<0> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn13 pad net078 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn31 pad net080 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXI49 vgnd_io tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| DD1 vcc_io vgnd_io dipw_dnw_v5 area=1558.740 pj=186.490 m=1 |
| DD0 vcc_io vssd ddnw_sub_v5 area=1791.380 pj=197.770 m=1 |
| RRM0 net070 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net078 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM3 net016 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM5 net057 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM6 net022 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM7 net076 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net068 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM4 net080 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_2_esd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_2_esd out_h out_vt pad vddio vssd vssio |
| *.PININFO out_h:B out_vt:B pad:B vddio:B vssd:B vssio:B |
| XXpddrvr_strong tie_lo_esd tie_lo_esd pad tie_lo_esd tie_lo_esd tie_lo_esd |
| + vddio vssio vssd vssio / s130iom0_gpio_pddrvr_strong_xres_2 |
| XXpudrvr_strong pad tie_hi_esd tie_hi_esd tie_hi_esd vddio vssd / |
| + s130iom0_gpio_pudrvr_strong |
| XXesd pad out_h out_vt vddio vssd vssd / s130iom0_gpio_buf_localesd |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_xres_2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_xres_2 amuxbus_a amuxbus_b out out_h pad vccd vcchib vdda |
| + vddio vddio_q vssa vssd vssio vssio_q vswitch |
| *.PININFO out:O out_h:O amuxbus_a:B amuxbus_b:B pad:B vccd:B vcchib:B vdda:B |
| *.PININFO vddio:B vddio_q:B vssa:B vssd:B vssio:B vssio_q:B vswitch:B |
| XXweakpullup pad vddio vssd / s130iom0_xres_wpu |
| XXibuf in_h in_vt out out_h vcchib vddio_q vssd / s130iom0_xres_ipath |
| XPAD0 pad pad_bond w=60 l=70 m=1 |
| XXxresesd in_h in_vt pad vddio vssd vssio / s130iom0_xres_2_esd |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_in_buf_xres2v2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_in_buf_xres2v2 in_h in_vt out_h out_h_n vcc_io vgnd vpwr |
| *.PININFO in_h:I in_vt:I vcc_io:I vgnd:I vpwr:I out_h:O out_h_n:O |
| MmI574 net_150 out_a net_34 vgnd nmos_v5 W=3 L=1 M=2 |
| MmI571 net_150 out_a vcc_io vgnd nmos_v5 W=1 L=1 M=1 |
| MmI598 net_150 out_a vcc_io vgnd nmos_v5 W=0.42 L=1 M=1 |
| Mmpd1 net_150 in_h net_158 vgnd nmos_v5 W=5 L=1 M=2 |
| MmI597 net_150 out_a net_34 vgnd nmos_v5 W=0.75 L=1 M=1 |
| MmI570 out_a in_h net_150 vgnd nmos_v5 W=5 L=0.5 M=3 |
| Mmpd_hrng net_150 in_vt net_158 vgnd nmos_v5 W=3 L=1 M=12 |
| Mmpden_1 net_158 tie_hi_esd vgnd vgnd nmos_v5 W=3 L=0.6 M=12 |
| Mmdis_trip_sel1 in_vt tie_hi_esd vgnd vgnd nmos_v5 W=3 L=1 M=1 |
| MmI592 out_h out_h_n vgnd vgnd nmos_v5 W=1 L=0.5 M=3 |
| Mmpu2 net_169 out_a vcc_io vcc_io pmos_v5 W=3 L=0.5 M=1 |
| MmI593 out_h out_h_n vcc_io vcc_io pmos_v5 W=3 L=0.5 M=3 |
| Mmpd2 net_169 out_a vgnd vgnd nmos_v5 W=1 L=0.5 M=2 |
| MmI589 out_h_n net_169 vgnd vgnd nmos_v5 W=1 L=0.5 M=2 |
| Mmpuen_2 out_a tie_hi_esd vcc_io vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI577 out_a vtrip_sel_h net_29 vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI590 out_h_n net_169 vcc_io vcc_io pmos_v5 W=3 L=0.5 M=2 |
| MmI584 net_118 net_118 net_117 vgnd nmos_nat_v5 W=1 L=0.9 M=1 |
| MmI585 net_117 net_117 out_a vgnd nmos_nat_v5 W=1 L=0.9 M=1 |
| Mmpu1_midopt net_034 in_h vcc_io vcc_io pmos_v5 W=5 L=0.8 M=2 |
| Mmpu1 net_034 in_h vcc_io vcc_io pmos_v5 W=7 L=0.8 M=3 |
| MmI575 vcc_io vtrip_sel_h net_34 vcc_io pmos_v5 W=0.75 L=0.5 M=2 |
| MmI567 net_29 in_h net_034 vcc_io pmos_v5 W=5 L=0.5 M=2 |
| MmI568 vgnd out_a net_034 vcc_io pmos_v5 W=0.75 L=2 M=1 |
| MmI578 out_a in_h net_025 vcc_io pmos_v5 W=5 L=0.5 M=4 |
| MmI579 net_025 in_h vcc_io vcc_io pmos_v5 W=7 L=0.8 M=1 |
| XXI599 vpwr net_147 / s130iom0_tk_tie_r_out_esd |
| XXI49 vcc_io tie_hi_esd / s130iom0_tk_tie_r_out_esd |
| MmI582 vgnd out_a net_025 vcc_io pmos_v5 W=5 L=1 M=1 |
| XXI576 tie_hi_esd vtrip_sel_h vgnd vcc_io / s130iom0_hvsbt_inv_x1 |
| MmI595 net_199 in_vt net_158 vgnd nmos_v5 W=3 L=1 M=8 |
| Mmpu1_mid_nat net_29 net_147 net_118 vgnd nmos_nat_v5 W=1 L=0.9 M=4 |
| RRM0 net_117 out_a 5.4m $[rm1] $W=0.23 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres_ipath_xres2v2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres_ipath_xres2v2 in_h in_vt out out_h vcchib vddio_q vssd |
| *.PININFO in_h:I in_vt:I out:O out_h:O vcchib:B vddio_q:B vssd:B |
| MmI35 out net_21 vssd vssd nmos W=1 L=0.25 M=8 |
| MmI33 out net_21 vcchib vcchib pmos_hvt W=3 L=0.25 M=4 |
| MmI34 net_21 net_78 vssd vssd nmos W=1 L=0.25 M=2 |
| XXhv_drv1 out_hysbuf_h out_h_n vssd vddio_q / s130iom0_hvsbt_inv_x1 |
| MmI32 net_21 net_78 vcchib vcchib pmos_hvt W=3 L=0.25 M=1 |
| XXhyst_buf out_rcfilt_h out_hysbuf_h vddio_q vssd / s130iom0_xres_inv_hys |
| XXhv_drv2 out_h_n out_h vssd vddio_q / s130iom0_hvsbt_inv_x4 |
| XXhv_lv_ls out_hysbuf_h net_062 net_78 vcchib vddio_q vssd / |
| + s130iom0_xres_hvlv_ls |
| XXgpio_inbuf in_h in_vt out_gpio_h net019 vddio_q vssd vcchib / |
| + s130iom0_gpio_in_buf_xres2v2 |
| XXrcfilt out_gpio_h out_rcfilt_h vddio_q vssd / s130iom0_xres2v2_rcfilter_lpf |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_gpio_pddrvr_strong_xres2v2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_gpio_pddrvr_strong_xres2v2 force_lo_h force_lovol_h pad |
| + pd_h<3> pd_h<2> tie_lo_esd vcc_io vgnd_io vssd vssio_amx |
| *.PININFO force_lo_h:I force_lovol_h:I pd_h<3>:I pd_h<2>:I vcc_io:I vgnd_io:I |
| *.PININFO vssio_amx:I tie_lo_esd:O pad:B vssd:B |
| XXn11<2> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<1> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn11<0> pad pd_h<2> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<2> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<1> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn32<0> pad net057 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<2> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<1> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn23<0> pad net068 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn22<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<2> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<1> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn21<0> pad pd_h<3> vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<2> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<1> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn24<0> pad net016 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn12 pad net070 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<2> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<1> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn33<0> pad net022 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<3> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<2> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<1> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn34<0> pad net076 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn13 pad net078 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXn31 pad net080 vgnd_io / s130iom0_com_pddrvr_unit_2_5 |
| XXI49 vgnd_io tie_lo_esd / s130iom0_tk_tie_r_out_esd |
| DD1 vcc_io vgnd_io dipw_dnw_v5 area=1558.740 pj=186.490 m=1 |
| DD0 vcc_io vssd ddnw_sub_v5 area=1791.380 pj=197.770 m=1 |
| RRM0 net070 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM1 net078 pd_h<2> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM3 net016 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM5 net057 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM6 net022 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM7 net076 tie_lo_esd 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM2 net068 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| RRM4 net080 pd_h<3> 1.9m $[rm2] $W=0.65 $L=0.01 M=1 |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_xres2v2_esd |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_xres2v2_esd out_h out_vt pad vddio vssd vssio |
| *.PININFO out_h:B out_vt:B pad:B vddio:B vssd:B vssio:B |
| XXpddrvr_strong tie_lo_esd tie_lo_esd pad tie_lo_esd tie_lo_esd tie_lo_esd |
| + vddio vssio vssd vssio / s130iom0_gpio_pddrvr_strong_xres2v2 |
| XXpudrvr_strong pad tie_hi_esd tie_hi_esd tie_hi_esd vddio vssd / |
| + s130iom0_gpio_pudrvr_strong |
| XXesd pad out_h out_vt vddio vssd vssd / s130iom0_gpio_buf_localesd |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: s130iom0_top_xres3v2 |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT s130iom0_top_xres3v2 amuxbus_a amuxbus_b pad pad_a_esd_h tie_weak_hi_h |
| + vccd vcchib vdda vddio vddio_q vssa vssd vssio vssio_q vswitch xres_h_n |
| + xres_n |
| *.PININFO xres_h_n:O xres_n:O amuxbus_a:B amuxbus_b:B pad:B pad_a_esd_h:B |
| *.PININFO tie_weak_hi_h:B vccd:B vcchib:B vdda:B vddio:B vddio_q:B vssa:B |
| *.PININFO vssd:B vssio:B vssio_q:B vswitch:B |
| XXesd_res pad pad_a_esd_h / s130_esd_res250only_small |
| XXweakpullup tie_weak_hi_h vddio vssd / s130iom0_xres_wpu |
| XXibuf in_h in_vt xres_n xres_h_n vcchib vddio_q vssd / |
| + s130iom0_xres_ipath_xres2v2 |
| XPAD0 pad pad_bond w=60 l=70 m=1 |
| XXxresesd in_h in_vt pad vddio vssd vssio / s130iom0_xres2v2_esd |
| .ENDS |
| |
| ************************************************************************ |
| * Library Name: s130iom0 |
| * Cell Name: ALL_Public_Cells |
| * View Name: schematic |
| ************************************************************************ |
| |
| .SUBCKT ALL_Public_Cells Is130iom0_analog_pad_amuxbus_a |
| + Is130iom0_analog_pad_amuxbus_b Is130iom0_analog_pad_pad |
| + Is130iom0_analog_pad_pad_core Is130iom0_analog_pad_vccd |
| + Is130iom0_analog_pad_vcchib Is130iom0_analog_pad_vdda |
| + Is130iom0_analog_pad_vddio Is130iom0_analog_pad_vddio_q |
| + Is130iom0_analog_pad_vssa Is130iom0_analog_pad_vssd |
| + Is130iom0_analog_pad_vssio Is130iom0_analog_pad_vssio_q |
| + Is130iom0_analog_pad_vswitch Is130iom0_top_amuxsplitv2_amuxbus_a_r |
| + Is130iom0_top_amuxsplitv2_amuxbus_b_r |
| + Is130iom0_top_amuxsplitv2_enable_vdda_h |
| + Is130iom0_top_amuxsplitv2_hld_vdda_h_n |
| + Is130iom0_top_amuxsplitv2_switch_aa_s0 |
| + Is130iom0_top_amuxsplitv2_switch_aa_sl |
| + Is130iom0_top_amuxsplitv2_switch_aa_sr |
| + Is130iom0_top_amuxsplitv2_switch_bb_s0 |
| + Is130iom0_top_amuxsplitv2_switch_bb_sl |
| + Is130iom0_top_amuxsplitv2_switch_bb_sr Is130iom0_top_amuxsplitv2_vccd |
| + Is130iom0_top_amuxsplitv2_vcchib Is130iom0_top_amuxsplitv2_vdda |
| + Is130iom0_top_amuxsplitv2_vddio Is130iom0_top_amuxsplitv2_vddio_q |
| + Is130iom0_top_amuxsplitv2_vssa Is130iom0_top_amuxsplitv2_vssd |
| + Is130iom0_top_amuxsplitv2_vssio Is130iom0_top_amuxsplitv2_vssio_q |
| + Is130iom0_top_amuxsplitv2_vswitch Is130iom0_top_axresv2_amuxbus_a |
| + Is130iom0_top_axresv2_amuxbus_b Is130iom0_top_axresv2_disable_pullup_h |
| + Is130iom0_top_axresv2_filter_in_h Is130iom0_top_axresv2_filter_out |
| + Is130iom0_top_axresv2_filter_out_h Is130iom0_top_axresv2_pullup_h |
| + Is130iom0_top_axresv2_tie_hi_esd Is130iom0_top_axresv2_tie_lo_esd |
| + Is130iom0_top_axresv2_vccd Is130iom0_top_axresv2_vcchib |
| + Is130iom0_top_axresv2_vdda Is130iom0_top_axresv2_vddio |
| + Is130iom0_top_axresv2_vddio_q Is130iom0_top_axresv2_vssa |
| + Is130iom0_top_axresv2_vssd Is130iom0_top_axresv2_vssio |
| + Is130iom0_top_axresv2_vssio_q Is130iom0_top_axresv2_vswitch |
| + Is130iom0_top_gpiov2_amuxbus_a Is130iom0_top_gpiov2_amuxbus_b |
| + Is130iom0_top_gpiov2_analog_en Is130iom0_top_gpiov2_analog_pol |
| + Is130iom0_top_gpiov2_analog_sel Is130iom0_top_gpiov2_dm<2> |
| + Is130iom0_top_gpiov2_dm<1> Is130iom0_top_gpiov2_dm<0> |
| + Is130iom0_top_gpiov2_enable_h Is130iom0_top_gpiov2_enable_inp_h |
| + Is130iom0_top_gpiov2_enable_vdda_h Is130iom0_top_gpiov2_enable_vddio |
| + Is130iom0_top_gpiov2_enable_vswitch_h Is130iom0_top_gpiov2_hld_h_n |
| + Is130iom0_top_gpiov2_hld_ovr Is130iom0_top_gpiov2_ib_mode_sel |
| + Is130iom0_top_gpiov2_in Is130iom0_top_gpiov2_in_h |
| + Is130iom0_top_gpiov2_inp_dis Is130iom0_top_gpiov2_oe_n |
| + Is130iom0_top_gpiov2_out Is130iom0_top_gpiov2_pad |
| + Is130iom0_top_gpiov2_pad_a_esd_0_h Is130iom0_top_gpiov2_pad_a_esd_1_h |
| + Is130iom0_top_gpiov2_pad_a_noesd_h Is130iom0_top_gpiov2_slow |
| + Is130iom0_top_gpiov2_tie_hi_esd Is130iom0_top_gpiov2_tie_lo_esd |
| + Is130iom0_top_gpiov2_vccd Is130iom0_top_gpiov2_vcchib |
| + Is130iom0_top_gpiov2_vdda Is130iom0_top_gpiov2_vddio |
| + Is130iom0_top_gpiov2_vddio_q Is130iom0_top_gpiov2_vssa |
| + Is130iom0_top_gpiov2_vssd Is130iom0_top_gpiov2_vssio |
| + Is130iom0_top_gpiov2_vssio_q Is130iom0_top_gpiov2_vswitch |
| + Is130iom0_top_gpiov2_vtrip_sel Is130iom0_top_gpiovrefv2_amuxbus_a |
| + Is130iom0_top_gpiovrefv2_amuxbus_b Is130iom0_top_gpiovrefv2_enable_h |
| + Is130iom0_top_gpiovrefv2_hld_h_n Is130iom0_top_gpiovrefv2_ref_sel<4> |
| + Is130iom0_top_gpiovrefv2_ref_sel<3> Is130iom0_top_gpiovrefv2_ref_sel<2> |
| + Is130iom0_top_gpiovrefv2_ref_sel<1> Is130iom0_top_gpiovrefv2_ref_sel<0> |
| + Is130iom0_top_gpiovrefv2_vccd Is130iom0_top_gpiovrefv2_vcchib |
| + Is130iom0_top_gpiovrefv2_vdda Is130iom0_top_gpiovrefv2_vddio |
| + Is130iom0_top_gpiovrefv2_vddio_q Is130iom0_top_gpiovrefv2_vinref |
| + Is130iom0_top_gpiovrefv2_vrefgen_en Is130iom0_top_gpiovrefv2_vssa |
| + Is130iom0_top_gpiovrefv2_vssd Is130iom0_top_gpiovrefv2_vssio |
| + Is130iom0_top_gpiovrefv2_vssio_q Is130iom0_top_gpiovrefv2_vswitch |
| + Is130iom0_top_ground_hvc_wpad_amuxbus_a |
| + Is130iom0_top_ground_hvc_wpad_amuxbus_b |
| + Is130iom0_top_ground_hvc_wpad_drn_hvc Is130iom0_top_ground_hvc_wpad_g_core |
| + Is130iom0_top_ground_hvc_wpad_g_pad Is130iom0_top_ground_hvc_wpad_ogc_hvc |
| + Is130iom0_top_ground_hvc_wpad_src_bdy_hvc Is130iom0_top_ground_hvc_wpad_vccd |
| + Is130iom0_top_ground_hvc_wpad_vcchib Is130iom0_top_ground_hvc_wpad_vdda |
| + Is130iom0_top_ground_hvc_wpad_vddio Is130iom0_top_ground_hvc_wpad_vddio_q |
| + Is130iom0_top_ground_hvc_wpad_vssa Is130iom0_top_ground_hvc_wpad_vssd |
| + Is130iom0_top_ground_hvc_wpad_vssio Is130iom0_top_ground_hvc_wpad_vssio_q |
| + Is130iom0_top_ground_hvc_wpad_vswitch |
| + Is130iom0_top_ground_lvc_wpad_amuxbus_a |
| + Is130iom0_top_ground_lvc_wpad_amuxbus_b |
| + Is130iom0_top_ground_lvc_wpad_bdy2_b2b |
| + Is130iom0_top_ground_lvc_wpad_drn_lvc1 |
| + Is130iom0_top_ground_lvc_wpad_drn_lvc2 Is130iom0_top_ground_lvc_wpad_g_core |
| + Is130iom0_top_ground_lvc_wpad_g_pad Is130iom0_top_ground_lvc_wpad_ogc_lvc |
| + Is130iom0_top_ground_lvc_wpad_src_bdy_lvc1 |
| + Is130iom0_top_ground_lvc_wpad_src_bdy_lvc2 |
| + Is130iom0_top_ground_lvc_wpad_vccd Is130iom0_top_ground_lvc_wpad_vcchib |
| + Is130iom0_top_ground_lvc_wpad_vdda Is130iom0_top_ground_lvc_wpad_vddio |
| + Is130iom0_top_ground_lvc_wpad_vddio_q Is130iom0_top_ground_lvc_wpad_vssa |
| + Is130iom0_top_ground_lvc_wpad_vssd Is130iom0_top_ground_lvc_wpad_vssio |
| + Is130iom0_top_ground_lvc_wpad_vssio_q Is130iom0_top_ground_lvc_wpad_vswitch |
| + Is130iom0_top_hvclamp_wopad_drn_hvc Is130iom0_top_hvclamp_wopad_ogc_hvc |
| + Is130iom0_top_hvclamp_wopad_src_bdy_hvc Is130iom0_top_lvc_b2b_wopad_bdy2_b2b |
| + Is130iom0_top_lvc_b2b_wopad_drn_lvc1 Is130iom0_top_lvc_b2b_wopad_drn_lvc2 |
| + Is130iom0_top_lvc_b2b_wopad_ogc_lvc Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc1 |
| + Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc2 Is130iom0_top_lvc_b2b_wopad_vssd |
| + Is130iom0_top_lvclamp_drn_lvc Is130iom0_top_lvclamp_ogc_lvc |
| + Is130iom0_top_lvclamp_src_bdy_lvc Is130iom0_top_power_hvc_wpad_amuxbus_a |
| + Is130iom0_top_power_hvc_wpad_amuxbus_b Is130iom0_top_power_hvc_wpad_drn_hvc |
| + Is130iom0_top_power_hvc_wpad_ogc_hvc Is130iom0_top_power_hvc_wpad_p_core |
| + Is130iom0_top_power_hvc_wpad_p_pad Is130iom0_top_power_hvc_wpad_src_bdy_hvc |
| + Is130iom0_top_power_hvc_wpad_vccd Is130iom0_top_power_hvc_wpad_vcchib |
| + Is130iom0_top_power_hvc_wpad_vdda Is130iom0_top_power_hvc_wpad_vddio |
| + Is130iom0_top_power_hvc_wpad_vddio_q Is130iom0_top_power_hvc_wpad_vssa |
| + Is130iom0_top_power_hvc_wpad_vssd Is130iom0_top_power_hvc_wpad_vssio |
| + Is130iom0_top_power_hvc_wpad_vssio_q Is130iom0_top_power_hvc_wpad_vswitch |
| + Is130iom0_top_power_lvc_wpad_amuxbus_a |
| + Is130iom0_top_power_lvc_wpad_amuxbus_b Is130iom0_top_power_lvc_wpad_bdy2_b2b |
| + Is130iom0_top_power_lvc_wpad_drn_lvc1 Is130iom0_top_power_lvc_wpad_drn_lvc2 |
| + Is130iom0_top_power_lvc_wpad_ogc_lvc Is130iom0_top_power_lvc_wpad_p_core |
| + Is130iom0_top_power_lvc_wpad_p_pad Is130iom0_top_power_lvc_wpad_src_bdy_lvc1 |
| + Is130iom0_top_power_lvc_wpad_src_bdy_lvc2 Is130iom0_top_power_lvc_wpad_vccd |
| + Is130iom0_top_power_lvc_wpad_vcchib Is130iom0_top_power_lvc_wpad_vdda |
| + Is130iom0_top_power_lvc_wpad_vddio Is130iom0_top_power_lvc_wpad_vddio_q |
| + Is130iom0_top_power_lvc_wpad_vssa Is130iom0_top_power_lvc_wpad_vssd |
| + Is130iom0_top_power_lvc_wpad_vssio Is130iom0_top_power_lvc_wpad_vssio_q |
| + Is130iom0_top_power_lvc_wpad_vswitch Is130iom0_top_pwrdetv2_in1_vddd_hv |
| + Is130iom0_top_pwrdetv2_in1_vddio_hv Is130iom0_top_pwrdetv2_in2_vddd_hv |
| + Is130iom0_top_pwrdetv2_in2_vddio_hv Is130iom0_top_pwrdetv2_in3_vddd_hv |
| + Is130iom0_top_pwrdetv2_in3_vddio_hv Is130iom0_top_pwrdetv2_out1_vddd_hv |
| + Is130iom0_top_pwrdetv2_out1_vddio_hv Is130iom0_top_pwrdetv2_out2_vddd_hv |
| + Is130iom0_top_pwrdetv2_out2_vddio_hv Is130iom0_top_pwrdetv2_out3_vddd_hv |
| + Is130iom0_top_pwrdetv2_out3_vddio_hv Is130iom0_top_pwrdetv2_rst_por_hv_n |
| + Is130iom0_top_pwrdetv2_tie_lo_esd Is130iom0_top_pwrdetv2_vccd |
| + Is130iom0_top_pwrdetv2_vddd1 Is130iom0_top_pwrdetv2_vddd2 |
| + Is130iom0_top_pwrdetv2_vddd_present_vddio_hv |
| + Is130iom0_top_pwrdetv2_vddio_present_vddd_hv Is130iom0_top_pwrdetv2_vddio_q |
| + Is130iom0_top_pwrdetv2_vssa Is130iom0_top_pwrdetv2_vssd |
| + Is130iom0_top_pwrdetv2_vssio_q Is130iom0_top_tp1_amuxbus_a |
| + Is130iom0_top_tp1_amuxbus_b Is130iom0_top_tp1_en_tp1 Is130iom0_top_tp1_tp1 |
| + Is130iom0_top_tp1_tp1_div Is130iom0_top_tp1_tp1_out Is130iom0_top_tp1_vccd |
| + Is130iom0_top_tp1_vcchib Is130iom0_top_tp1_vdda Is130iom0_top_tp1_vddio |
| + Is130iom0_top_tp1_vddio_q Is130iom0_top_tp1_vssa Is130iom0_top_tp1_vssd |
| + Is130iom0_top_tp1_vssio Is130iom0_top_tp1_vssio_q Is130iom0_top_tp1_vswitch |
| + Is130iom0_top_tp2_amuxbus_a Is130iom0_top_tp2_amuxbus_b |
| + Is130iom0_top_tp2_en_tp2 Is130iom0_top_tp2_tp2 Is130iom0_top_tp2_tp2_div |
| + Is130iom0_top_tp2_tp2_out Is130iom0_top_tp2_vccd Is130iom0_top_tp2_vcchib |
| + Is130iom0_top_tp2_vdda Is130iom0_top_tp2_vddio Is130iom0_top_tp2_vddio_q |
| + Is130iom0_top_tp2_vneg Is130iom0_top_tp2_vssa Is130iom0_top_tp2_vssd |
| + Is130iom0_top_tp2_vssio Is130iom0_top_tp2_vssio_q Is130iom0_top_tp2_vswitch |
| + Is130iom0_top_tp3_tp3 Is130iom0_top_tp3_tp3_out Is130iom0_top_tp3_vddd |
| + Is130iom0_top_tp3_vssd Is130iom0_top_vrefcapv2_amuxbus_a |
| + Is130iom0_top_vrefcapv2_amuxbus_b Is130iom0_top_vrefcapv2_cneg |
| + Is130iom0_top_vrefcapv2_cpos Is130iom0_top_vrefcapv2_vccd |
| + Is130iom0_top_vrefcapv2_vcchib Is130iom0_top_vrefcapv2_vdda |
| + Is130iom0_top_vrefcapv2_vddio Is130iom0_top_vrefcapv2_vddio_q |
| + Is130iom0_top_vrefcapv2_vssa Is130iom0_top_vrefcapv2_vssd |
| + Is130iom0_top_vrefcapv2_vssio Is130iom0_top_vrefcapv2_vssio_q |
| + Is130iom0_top_vrefcapv2_vswitch Is130iom0_top_xres3v2_amuxbus_a |
| + Is130iom0_top_xres3v2_amuxbus_b Is130iom0_top_xres3v2_pad |
| + Is130iom0_top_xres3v2_pad_a_esd_h Is130iom0_top_xres3v2_tie_weak_hi_h |
| + Is130iom0_top_xres3v2_vccd Is130iom0_top_xres3v2_vcchib |
| + Is130iom0_top_xres3v2_vdda Is130iom0_top_xres3v2_vddio |
| + Is130iom0_top_xres3v2_vddio_q Is130iom0_top_xres3v2_vssa |
| + Is130iom0_top_xres3v2_vssd Is130iom0_top_xres3v2_vssio |
| + Is130iom0_top_xres3v2_vssio_q Is130iom0_top_xres3v2_vswitch |
| + Is130iom0_top_xres3v2_xres_h_n Is130iom0_top_xres3v2_xres_n |
| + Is130iom0_top_xres_2_amuxbus_a Is130iom0_top_xres_2_amuxbus_b |
| + Is130iom0_top_xres_2_out Is130iom0_top_xres_2_out_h Is130iom0_top_xres_2_pad |
| + Is130iom0_top_xres_2_vccd Is130iom0_top_xres_2_vcchib |
| + Is130iom0_top_xres_2_vdda Is130iom0_top_xres_2_vddio |
| + Is130iom0_top_xres_2_vddio_q Is130iom0_top_xres_2_vssa |
| + Is130iom0_top_xres_2_vssd Is130iom0_top_xres_2_vssio |
| + Is130iom0_top_xres_2_vssio_q Is130iom0_top_xres_2_vswitch |
| + Is130iom0_top_xres_amuxbus_a Is130iom0_top_xres_amuxbus_b |
| + Is130iom0_top_xres_out Is130iom0_top_xres_out_h Is130iom0_top_xres_pad |
| + Is130iom0_top_xres_vccd Is130iom0_top_xres_vcchib Is130iom0_top_xres_vdda |
| + Is130iom0_top_xres_vddio Is130iom0_top_xres_vddio_q Is130iom0_top_xres_vssa |
| + Is130iom0_top_xres_vssd Is130iom0_top_xres_vssio Is130iom0_top_xres_vssio_q |
| + Is130iom0_top_xres_vswitch |
| *.PININFO Is130iom0_top_amuxsplitv2_enable_vdda_h:I |
| *.PININFO Is130iom0_top_amuxsplitv2_hld_vdda_h_n:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_aa_s0:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_aa_sl:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_aa_sr:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_bb_s0:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_bb_sl:I |
| *.PININFO Is130iom0_top_amuxsplitv2_switch_bb_sr:I |
| *.PININFO Is130iom0_top_axresv2_disable_pullup_h:I |
| *.PININFO Is130iom0_top_axresv2_filter_in_h:I Is130iom0_top_gpiov2_analog_en:I |
| *.PININFO Is130iom0_top_gpiov2_analog_pol:I Is130iom0_top_gpiov2_analog_sel:I |
| *.PININFO Is130iom0_top_gpiov2_dm<2>:I Is130iom0_top_gpiov2_dm<1>:I |
| *.PININFO Is130iom0_top_gpiov2_dm<0>:I Is130iom0_top_gpiov2_enable_h:I |
| *.PININFO Is130iom0_top_gpiov2_enable_inp_h:I |
| *.PININFO Is130iom0_top_gpiov2_enable_vdda_h:I |
| *.PININFO Is130iom0_top_gpiov2_enable_vddio:I |
| *.PININFO Is130iom0_top_gpiov2_enable_vswitch_h:I |
| *.PININFO Is130iom0_top_gpiov2_hld_h_n:I Is130iom0_top_gpiov2_hld_ovr:I |
| *.PININFO Is130iom0_top_gpiov2_ib_mode_sel:I Is130iom0_top_gpiov2_inp_dis:I |
| *.PININFO Is130iom0_top_gpiov2_oe_n:I Is130iom0_top_gpiov2_out:I |
| *.PININFO Is130iom0_top_gpiov2_slow:I Is130iom0_top_gpiov2_vtrip_sel:I |
| *.PININFO Is130iom0_top_gpiovrefv2_enable_h:I |
| *.PININFO Is130iom0_top_gpiovrefv2_hld_h_n:I |
| *.PININFO Is130iom0_top_gpiovrefv2_ref_sel<4>:I |
| *.PININFO Is130iom0_top_gpiovrefv2_ref_sel<3>:I |
| *.PININFO Is130iom0_top_gpiovrefv2_ref_sel<2>:I |
| *.PININFO Is130iom0_top_gpiovrefv2_ref_sel<1>:I |
| *.PININFO Is130iom0_top_gpiovrefv2_ref_sel<0>:I |
| *.PININFO Is130iom0_top_gpiovrefv2_vrefgen_en:I |
| *.PININFO Is130iom0_top_pwrdetv2_in1_vddd_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_in1_vddio_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_in2_vddd_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_in2_vddio_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_in3_vddd_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_in3_vddio_hv:I |
| *.PININFO Is130iom0_top_pwrdetv2_rst_por_hv_n:I Is130iom0_top_tp1_en_tp1:I |
| *.PININFO Is130iom0_top_tp2_en_tp2:I Is130iom0_top_axresv2_filter_out:O |
| *.PININFO Is130iom0_top_axresv2_filter_out_h:O |
| *.PININFO Is130iom0_top_axresv2_tie_hi_esd:O |
| *.PININFO Is130iom0_top_axresv2_tie_lo_esd:O Is130iom0_top_gpiov2_in:O |
| *.PININFO Is130iom0_top_gpiov2_in_h:O Is130iom0_top_gpiov2_tie_hi_esd:O |
| *.PININFO Is130iom0_top_gpiov2_tie_lo_esd:O |
| *.PININFO Is130iom0_top_pwrdetv2_out1_vddd_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_out1_vddio_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_out2_vddd_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_out2_vddio_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_out3_vddd_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_out3_vddio_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_tie_lo_esd:O |
| *.PININFO Is130iom0_top_pwrdetv2_vddd_present_vddio_hv:O |
| *.PININFO Is130iom0_top_pwrdetv2_vddio_present_vddd_hv:O |
| *.PININFO Is130iom0_top_tp1_tp1_div:O Is130iom0_top_tp2_tp2_div:O |
| *.PININFO Is130iom0_top_xres3v2_xres_h_n:O Is130iom0_top_xres3v2_xres_n:O |
| *.PININFO Is130iom0_top_xres_2_out:O Is130iom0_top_xres_2_out_h:O |
| *.PININFO Is130iom0_top_xres_out:O Is130iom0_top_xres_out_h:O |
| *.PININFO Is130iom0_analog_pad_amuxbus_a:B Is130iom0_analog_pad_amuxbus_b:B |
| *.PININFO Is130iom0_analog_pad_pad:B Is130iom0_analog_pad_pad_core:B |
| *.PININFO Is130iom0_analog_pad_vccd:B Is130iom0_analog_pad_vcchib:B |
| *.PININFO Is130iom0_analog_pad_vdda:B Is130iom0_analog_pad_vddio:B |
| *.PININFO Is130iom0_analog_pad_vddio_q:B Is130iom0_analog_pad_vssa:B |
| *.PININFO Is130iom0_analog_pad_vssd:B Is130iom0_analog_pad_vssio:B |
| *.PININFO Is130iom0_analog_pad_vssio_q:B Is130iom0_analog_pad_vswitch:B |
| *.PININFO Is130iom0_top_amuxsplitv2_amuxbus_a_r:B |
| *.PININFO Is130iom0_top_amuxsplitv2_amuxbus_b_r:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vccd:B Is130iom0_top_amuxsplitv2_vcchib:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vdda:B Is130iom0_top_amuxsplitv2_vddio:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vddio_q:B Is130iom0_top_amuxsplitv2_vssa:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vssd:B Is130iom0_top_amuxsplitv2_vssio:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vssio_q:B |
| *.PININFO Is130iom0_top_amuxsplitv2_vswitch:B |
| *.PININFO Is130iom0_top_axresv2_amuxbus_a:B Is130iom0_top_axresv2_amuxbus_b:B |
| *.PININFO Is130iom0_top_axresv2_pullup_h:B Is130iom0_top_axresv2_vccd:B |
| *.PININFO Is130iom0_top_axresv2_vcchib:B Is130iom0_top_axresv2_vdda:B |
| *.PININFO Is130iom0_top_axresv2_vddio:B Is130iom0_top_axresv2_vddio_q:B |
| *.PININFO Is130iom0_top_axresv2_vssa:B Is130iom0_top_axresv2_vssd:B |
| *.PININFO Is130iom0_top_axresv2_vssio:B Is130iom0_top_axresv2_vssio_q:B |
| *.PININFO Is130iom0_top_axresv2_vswitch:B Is130iom0_top_gpiov2_amuxbus_a:B |
| *.PININFO Is130iom0_top_gpiov2_amuxbus_b:B Is130iom0_top_gpiov2_pad:B |
| *.PININFO Is130iom0_top_gpiov2_pad_a_esd_0_h:B |
| *.PININFO Is130iom0_top_gpiov2_pad_a_esd_1_h:B |
| *.PININFO Is130iom0_top_gpiov2_pad_a_noesd_h:B Is130iom0_top_gpiov2_vccd:B |
| *.PININFO Is130iom0_top_gpiov2_vcchib:B Is130iom0_top_gpiov2_vdda:B |
| *.PININFO Is130iom0_top_gpiov2_vddio:B Is130iom0_top_gpiov2_vddio_q:B |
| *.PININFO Is130iom0_top_gpiov2_vssa:B Is130iom0_top_gpiov2_vssd:B |
| *.PININFO Is130iom0_top_gpiov2_vssio:B Is130iom0_top_gpiov2_vssio_q:B |
| *.PININFO Is130iom0_top_gpiov2_vswitch:B Is130iom0_top_gpiovrefv2_amuxbus_a:B |
| *.PININFO Is130iom0_top_gpiovrefv2_amuxbus_b:B Is130iom0_top_gpiovrefv2_vccd:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vcchib:B Is130iom0_top_gpiovrefv2_vdda:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vddio:B Is130iom0_top_gpiovrefv2_vddio_q:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vinref:B Is130iom0_top_gpiovrefv2_vssa:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vssd:B Is130iom0_top_gpiovrefv2_vssio:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vssio_q:B |
| *.PININFO Is130iom0_top_gpiovrefv2_vswitch:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_amuxbus_a:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_amuxbus_b:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_drn_hvc:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_g_core:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_g_pad:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_ogc_hvc:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_src_bdy_hvc:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vccd:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vcchib:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vdda:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vddio:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vddio_q:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vssa:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vssd:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vssio:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vssio_q:B |
| *.PININFO Is130iom0_top_ground_hvc_wpad_vswitch:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_amuxbus_a:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_amuxbus_b:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_bdy2_b2b:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_drn_lvc1:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_drn_lvc2:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_g_core:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_g_pad:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_ogc_lvc:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_src_bdy_lvc1:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_src_bdy_lvc2:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vccd:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vcchib:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vdda:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vddio:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vddio_q:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vssa:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vssd:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vssio:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vssio_q:B |
| *.PININFO Is130iom0_top_ground_lvc_wpad_vswitch:B |
| *.PININFO Is130iom0_top_hvclamp_wopad_drn_hvc:B |
| *.PININFO Is130iom0_top_hvclamp_wopad_ogc_hvc:B |
| *.PININFO Is130iom0_top_hvclamp_wopad_src_bdy_hvc:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_bdy2_b2b:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_drn_lvc1:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_drn_lvc2:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_ogc_lvc:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc1:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc2:B |
| *.PININFO Is130iom0_top_lvc_b2b_wopad_vssd:B Is130iom0_top_lvclamp_drn_lvc:B |
| *.PININFO Is130iom0_top_lvclamp_ogc_lvc:B Is130iom0_top_lvclamp_src_bdy_lvc:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_amuxbus_a:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_amuxbus_b:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_drn_hvc:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_ogc_hvc:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_p_core:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_p_pad:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_src_bdy_hvc:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vccd:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vcchib:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vdda:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vddio:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vddio_q:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vssa:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vssd:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vssio:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vssio_q:B |
| *.PININFO Is130iom0_top_power_hvc_wpad_vswitch:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_amuxbus_a:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_amuxbus_b:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_bdy2_b2b:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_drn_lvc1:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_drn_lvc2:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_ogc_lvc:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_p_core:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_p_pad:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_src_bdy_lvc1:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_src_bdy_lvc2:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vccd:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vcchib:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vdda:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vddio:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vddio_q:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vssa:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vssd:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vssio:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vssio_q:B |
| *.PININFO Is130iom0_top_power_lvc_wpad_vswitch:B Is130iom0_top_pwrdetv2_vccd:B |
| *.PININFO Is130iom0_top_pwrdetv2_vddd1:B Is130iom0_top_pwrdetv2_vddd2:B |
| *.PININFO Is130iom0_top_pwrdetv2_vddio_q:B Is130iom0_top_pwrdetv2_vssa:B |
| *.PININFO Is130iom0_top_pwrdetv2_vssd:B Is130iom0_top_pwrdetv2_vssio_q:B |
| *.PININFO Is130iom0_top_tp1_amuxbus_a:B Is130iom0_top_tp1_amuxbus_b:B |
| *.PININFO Is130iom0_top_tp1_tp1:B Is130iom0_top_tp1_tp1_out:B |
| *.PININFO Is130iom0_top_tp1_vccd:B Is130iom0_top_tp1_vcchib:B |
| *.PININFO Is130iom0_top_tp1_vdda:B Is130iom0_top_tp1_vddio:B |
| *.PININFO Is130iom0_top_tp1_vddio_q:B Is130iom0_top_tp1_vssa:B |
| *.PININFO Is130iom0_top_tp1_vssd:B Is130iom0_top_tp1_vssio:B |
| *.PININFO Is130iom0_top_tp1_vssio_q:B Is130iom0_top_tp1_vswitch:B |
| *.PININFO Is130iom0_top_tp2_amuxbus_a:B Is130iom0_top_tp2_amuxbus_b:B |
| *.PININFO Is130iom0_top_tp2_tp2:B Is130iom0_top_tp2_tp2_out:B |
| *.PININFO Is130iom0_top_tp2_vccd:B Is130iom0_top_tp2_vcchib:B |
| *.PININFO Is130iom0_top_tp2_vdda:B Is130iom0_top_tp2_vddio:B |
| *.PININFO Is130iom0_top_tp2_vddio_q:B Is130iom0_top_tp2_vneg:B |
| *.PININFO Is130iom0_top_tp2_vssa:B Is130iom0_top_tp2_vssd:B |
| *.PININFO Is130iom0_top_tp2_vssio:B Is130iom0_top_tp2_vssio_q:B |
| *.PININFO Is130iom0_top_tp2_vswitch:B Is130iom0_top_tp3_tp3:B |
| *.PININFO Is130iom0_top_tp3_tp3_out:B Is130iom0_top_tp3_vddd:B |
| *.PININFO Is130iom0_top_tp3_vssd:B Is130iom0_top_vrefcapv2_amuxbus_a:B |
| *.PININFO Is130iom0_top_vrefcapv2_amuxbus_b:B Is130iom0_top_vrefcapv2_cneg:B |
| *.PININFO Is130iom0_top_vrefcapv2_cpos:B Is130iom0_top_vrefcapv2_vccd:B |
| *.PININFO Is130iom0_top_vrefcapv2_vcchib:B Is130iom0_top_vrefcapv2_vdda:B |
| *.PININFO Is130iom0_top_vrefcapv2_vddio:B Is130iom0_top_vrefcapv2_vddio_q:B |
| *.PININFO Is130iom0_top_vrefcapv2_vssa:B Is130iom0_top_vrefcapv2_vssd:B |
| *.PININFO Is130iom0_top_vrefcapv2_vssio:B Is130iom0_top_vrefcapv2_vssio_q:B |
| *.PININFO Is130iom0_top_vrefcapv2_vswitch:B Is130iom0_top_xres3v2_amuxbus_a:B |
| *.PININFO Is130iom0_top_xres3v2_amuxbus_b:B Is130iom0_top_xres3v2_pad:B |
| *.PININFO Is130iom0_top_xres3v2_pad_a_esd_h:B |
| *.PININFO Is130iom0_top_xres3v2_tie_weak_hi_h:B Is130iom0_top_xres3v2_vccd:B |
| *.PININFO Is130iom0_top_xres3v2_vcchib:B Is130iom0_top_xres3v2_vdda:B |
| *.PININFO Is130iom0_top_xres3v2_vddio:B Is130iom0_top_xres3v2_vddio_q:B |
| *.PININFO Is130iom0_top_xres3v2_vssa:B Is130iom0_top_xres3v2_vssd:B |
| *.PININFO Is130iom0_top_xres3v2_vssio:B Is130iom0_top_xres3v2_vssio_q:B |
| *.PININFO Is130iom0_top_xres3v2_vswitch:B Is130iom0_top_xres_2_amuxbus_a:B |
| *.PININFO Is130iom0_top_xres_2_amuxbus_b:B Is130iom0_top_xres_2_pad:B |
| *.PININFO Is130iom0_top_xres_2_vccd:B Is130iom0_top_xres_2_vcchib:B |
| *.PININFO Is130iom0_top_xres_2_vdda:B Is130iom0_top_xres_2_vddio:B |
| *.PININFO Is130iom0_top_xres_2_vddio_q:B Is130iom0_top_xres_2_vssa:B |
| *.PININFO Is130iom0_top_xres_2_vssd:B Is130iom0_top_xres_2_vssio:B |
| *.PININFO Is130iom0_top_xres_2_vssio_q:B Is130iom0_top_xres_2_vswitch:B |
| *.PININFO Is130iom0_top_xres_amuxbus_a:B Is130iom0_top_xres_amuxbus_b:B |
| *.PININFO Is130iom0_top_xres_pad:B Is130iom0_top_xres_vccd:B |
| *.PININFO Is130iom0_top_xres_vcchib:B Is130iom0_top_xres_vdda:B |
| *.PININFO Is130iom0_top_xres_vddio:B Is130iom0_top_xres_vddio_q:B |
| *.PININFO Is130iom0_top_xres_vssa:B Is130iom0_top_xres_vssd:B |
| *.PININFO Is130iom0_top_xres_vssio:B Is130iom0_top_xres_vssio_q:B |
| *.PININFO Is130iom0_top_xres_vswitch:B |
| XIs130iom0_analog_pad Is130iom0_analog_pad_amuxbus_a |
| + Is130iom0_analog_pad_amuxbus_b Is130iom0_analog_pad_pad |
| + Is130iom0_analog_pad_pad_core Is130iom0_analog_pad_vccd |
| + Is130iom0_analog_pad_vcchib Is130iom0_analog_pad_vdda |
| + Is130iom0_analog_pad_vddio Is130iom0_analog_pad_vddio_q |
| + Is130iom0_analog_pad_vssa Is130iom0_analog_pad_vssd |
| + Is130iom0_analog_pad_vssio Is130iom0_analog_pad_vssio_q |
| + Is130iom0_analog_pad_vswitch / s130iom0_analog_pad |
| XIs130iom0_top_amuxsplitv2 Is130iom0_top_amuxsplitv2_amuxbus_a_r |
| + Is130iom0_top_amuxsplitv2_amuxbus_a_r Is130iom0_top_amuxsplitv2_amuxbus_b_r |
| + Is130iom0_top_amuxsplitv2_amuxbus_b_r |
| + Is130iom0_top_amuxsplitv2_enable_vdda_h |
| + Is130iom0_top_amuxsplitv2_hld_vdda_h_n |
| + Is130iom0_top_amuxsplitv2_switch_aa_s0 |
| + Is130iom0_top_amuxsplitv2_switch_aa_sl |
| + Is130iom0_top_amuxsplitv2_switch_aa_sr |
| + Is130iom0_top_amuxsplitv2_switch_bb_s0 |
| + Is130iom0_top_amuxsplitv2_switch_bb_sl |
| + Is130iom0_top_amuxsplitv2_switch_bb_sr Is130iom0_top_amuxsplitv2_vccd |
| + Is130iom0_top_amuxsplitv2_vcchib Is130iom0_top_amuxsplitv2_vdda |
| + Is130iom0_top_amuxsplitv2_vddio Is130iom0_top_amuxsplitv2_vddio_q |
| + Is130iom0_top_amuxsplitv2_vssa Is130iom0_top_amuxsplitv2_vssd |
| + Is130iom0_top_amuxsplitv2_vssio Is130iom0_top_amuxsplitv2_vssio_q |
| + Is130iom0_top_amuxsplitv2_vswitch / s130iom0_top_amuxsplitv2 |
| XIs130iom0_top_axresv2 Is130iom0_top_axresv2_amuxbus_a |
| + Is130iom0_top_axresv2_amuxbus_b Is130iom0_top_axresv2_disable_pullup_h |
| + Is130iom0_top_axresv2_filter_in_h Is130iom0_top_axresv2_filter_out |
| + Is130iom0_top_axresv2_filter_out_h Is130iom0_top_axresv2_pullup_h |
| + Is130iom0_top_axresv2_tie_hi_esd Is130iom0_top_axresv2_tie_lo_esd |
| + Is130iom0_top_axresv2_vccd Is130iom0_top_axresv2_vcchib |
| + Is130iom0_top_axresv2_vdda Is130iom0_top_axresv2_vddio |
| + Is130iom0_top_axresv2_vddio_q Is130iom0_top_axresv2_vssa |
| + Is130iom0_top_axresv2_vssd Is130iom0_top_axresv2_vssio |
| + Is130iom0_top_axresv2_vssio_q Is130iom0_top_axresv2_vswitch / |
| + s130iom0_top_axresv2 |
| XIs130iom0_top_gpiov2 Is130iom0_top_gpiov2_amuxbus_a |
| + Is130iom0_top_gpiov2_amuxbus_b Is130iom0_top_gpiov2_analog_en |
| + Is130iom0_top_gpiov2_analog_pol Is130iom0_top_gpiov2_analog_sel |
| + Is130iom0_top_gpiov2_dm<2> Is130iom0_top_gpiov2_dm<1> |
| + Is130iom0_top_gpiov2_dm<0> Is130iom0_top_gpiov2_enable_h |
| + Is130iom0_top_gpiov2_enable_inp_h Is130iom0_top_gpiov2_enable_vdda_h |
| + Is130iom0_top_gpiov2_enable_vddio Is130iom0_top_gpiov2_enable_vswitch_h |
| + Is130iom0_top_gpiov2_hld_h_n Is130iom0_top_gpiov2_hld_ovr |
| + Is130iom0_top_gpiov2_ib_mode_sel Is130iom0_top_gpiov2_in |
| + Is130iom0_top_gpiov2_in_h Is130iom0_top_gpiov2_inp_dis |
| + Is130iom0_top_gpiov2_oe_n Is130iom0_top_gpiov2_out Is130iom0_top_gpiov2_pad |
| + Is130iom0_top_gpiov2_pad_a_esd_0_h Is130iom0_top_gpiov2_pad_a_esd_1_h |
| + Is130iom0_top_gpiov2_pad_a_noesd_h Is130iom0_top_gpiov2_slow |
| + Is130iom0_top_gpiov2_tie_hi_esd Is130iom0_top_gpiov2_tie_lo_esd |
| + Is130iom0_top_gpiov2_vccd Is130iom0_top_gpiov2_vcchib |
| + Is130iom0_top_gpiov2_vdda Is130iom0_top_gpiov2_vddio |
| + Is130iom0_top_gpiov2_vddio_q Is130iom0_top_gpiov2_vssa |
| + Is130iom0_top_gpiov2_vssd Is130iom0_top_gpiov2_vssio |
| + Is130iom0_top_gpiov2_vssio_q Is130iom0_top_gpiov2_vswitch |
| + Is130iom0_top_gpiov2_vtrip_sel / s130iom0_top_gpiov2 |
| XIs130iom0_top_gpiovrefv2 Is130iom0_top_gpiovrefv2_amuxbus_a |
| + Is130iom0_top_gpiovrefv2_amuxbus_b Is130iom0_top_gpiovrefv2_enable_h |
| + Is130iom0_top_gpiovrefv2_hld_h_n Is130iom0_top_gpiovrefv2_ref_sel<4> |
| + Is130iom0_top_gpiovrefv2_ref_sel<3> Is130iom0_top_gpiovrefv2_ref_sel<2> |
| + Is130iom0_top_gpiovrefv2_ref_sel<1> Is130iom0_top_gpiovrefv2_ref_sel<0> |
| + Is130iom0_top_gpiovrefv2_vccd Is130iom0_top_gpiovrefv2_vcchib |
| + Is130iom0_top_gpiovrefv2_vdda Is130iom0_top_gpiovrefv2_vddio |
| + Is130iom0_top_gpiovrefv2_vddio_q Is130iom0_top_gpiovrefv2_vinref |
| + Is130iom0_top_gpiovrefv2_vrefgen_en Is130iom0_top_gpiovrefv2_vssa |
| + Is130iom0_top_gpiovrefv2_vssd Is130iom0_top_gpiovrefv2_vssio |
| + Is130iom0_top_gpiovrefv2_vssio_q Is130iom0_top_gpiovrefv2_vswitch / |
| + s130iom0_top_gpiovrefv2 |
| XIs130iom0_top_ground_hvc_wpad Is130iom0_top_ground_hvc_wpad_amuxbus_a |
| + Is130iom0_top_ground_hvc_wpad_amuxbus_b |
| + Is130iom0_top_ground_hvc_wpad_drn_hvc Is130iom0_top_ground_hvc_wpad_g_core |
| + Is130iom0_top_ground_hvc_wpad_g_pad Is130iom0_top_ground_hvc_wpad_ogc_hvc |
| + Is130iom0_top_ground_hvc_wpad_src_bdy_hvc Is130iom0_top_ground_hvc_wpad_vccd |
| + Is130iom0_top_ground_hvc_wpad_vcchib Is130iom0_top_ground_hvc_wpad_vdda |
| + Is130iom0_top_ground_hvc_wpad_vddio Is130iom0_top_ground_hvc_wpad_vddio_q |
| + Is130iom0_top_ground_hvc_wpad_vssa Is130iom0_top_ground_hvc_wpad_vssd |
| + Is130iom0_top_ground_hvc_wpad_vssio Is130iom0_top_ground_hvc_wpad_vssio_q |
| + Is130iom0_top_ground_hvc_wpad_vswitch / s130iom0_top_ground_hvc_wpad |
| XIs130iom0_top_ground_lvc_wpad Is130iom0_top_ground_lvc_wpad_amuxbus_a |
| + Is130iom0_top_ground_lvc_wpad_amuxbus_b |
| + Is130iom0_top_ground_lvc_wpad_bdy2_b2b |
| + Is130iom0_top_ground_lvc_wpad_drn_lvc1 |
| + Is130iom0_top_ground_lvc_wpad_drn_lvc2 Is130iom0_top_ground_lvc_wpad_g_core |
| + Is130iom0_top_ground_lvc_wpad_g_pad Is130iom0_top_ground_lvc_wpad_ogc_lvc |
| + Is130iom0_top_ground_lvc_wpad_src_bdy_lvc1 |
| + Is130iom0_top_ground_lvc_wpad_src_bdy_lvc2 |
| + Is130iom0_top_ground_lvc_wpad_vccd Is130iom0_top_ground_lvc_wpad_vcchib |
| + Is130iom0_top_ground_lvc_wpad_vdda Is130iom0_top_ground_lvc_wpad_vddio |
| + Is130iom0_top_ground_lvc_wpad_vddio_q Is130iom0_top_ground_lvc_wpad_vssa |
| + Is130iom0_top_ground_lvc_wpad_vssd Is130iom0_top_ground_lvc_wpad_vssio |
| + Is130iom0_top_ground_lvc_wpad_vssio_q Is130iom0_top_ground_lvc_wpad_vswitch |
| + / s130iom0_top_ground_lvc_wpad |
| XIs130iom0_top_hvclamp_wopad Is130iom0_top_hvclamp_wopad_drn_hvc |
| + Is130iom0_top_hvclamp_wopad_ogc_hvc Is130iom0_top_hvclamp_wopad_src_bdy_hvc |
| + / s130iom0_top_hvclamp_wopad |
| XIs130iom0_top_lvc_b2b_wopad Is130iom0_top_lvc_b2b_wopad_bdy2_b2b |
| + Is130iom0_top_lvc_b2b_wopad_drn_lvc1 Is130iom0_top_lvc_b2b_wopad_drn_lvc2 |
| + Is130iom0_top_lvc_b2b_wopad_ogc_lvc Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc1 |
| + Is130iom0_top_lvc_b2b_wopad_src_bdy_lvc2 Is130iom0_top_lvc_b2b_wopad_vssd / |
| + s130iom0_top_lvc_b2b_wopad |
| XIs130iom0_top_lvclamp Is130iom0_top_lvclamp_drn_lvc |
| + Is130iom0_top_lvclamp_ogc_lvc Is130iom0_top_lvclamp_src_bdy_lvc / |
| + s130iom0_top_lvclamp |
| XIs130iom0_top_power_hvc_wpad Is130iom0_top_power_hvc_wpad_amuxbus_a |
| + Is130iom0_top_power_hvc_wpad_amuxbus_b Is130iom0_top_power_hvc_wpad_drn_hvc |
| + Is130iom0_top_power_hvc_wpad_ogc_hvc Is130iom0_top_power_hvc_wpad_p_core |
| + Is130iom0_top_power_hvc_wpad_p_pad Is130iom0_top_power_hvc_wpad_src_bdy_hvc |
| + Is130iom0_top_power_hvc_wpad_vccd Is130iom0_top_power_hvc_wpad_vcchib |
| + Is130iom0_top_power_hvc_wpad_vdda Is130iom0_top_power_hvc_wpad_vddio |
| + Is130iom0_top_power_hvc_wpad_vddio_q Is130iom0_top_power_hvc_wpad_vssa |
| + Is130iom0_top_power_hvc_wpad_vssd Is130iom0_top_power_hvc_wpad_vssio |
| + Is130iom0_top_power_hvc_wpad_vssio_q Is130iom0_top_power_hvc_wpad_vswitch / |
| + s130iom0_top_power_hvc_wpad |
| XIs130iom0_top_power_lvc_wpad Is130iom0_top_power_lvc_wpad_amuxbus_a |
| + Is130iom0_top_power_lvc_wpad_amuxbus_b Is130iom0_top_power_lvc_wpad_bdy2_b2b |
| + Is130iom0_top_power_lvc_wpad_drn_lvc1 Is130iom0_top_power_lvc_wpad_drn_lvc2 |
| + Is130iom0_top_power_lvc_wpad_ogc_lvc Is130iom0_top_power_lvc_wpad_p_core |
| + Is130iom0_top_power_lvc_wpad_p_pad Is130iom0_top_power_lvc_wpad_src_bdy_lvc1 |
| + Is130iom0_top_power_lvc_wpad_src_bdy_lvc2 Is130iom0_top_power_lvc_wpad_vccd |
| + Is130iom0_top_power_lvc_wpad_vcchib Is130iom0_top_power_lvc_wpad_vdda |
| + Is130iom0_top_power_lvc_wpad_vddio Is130iom0_top_power_lvc_wpad_vddio_q |
| + Is130iom0_top_power_lvc_wpad_vssa Is130iom0_top_power_lvc_wpad_vssd |
| + Is130iom0_top_power_lvc_wpad_vssio Is130iom0_top_power_lvc_wpad_vssio_q |
| + Is130iom0_top_power_lvc_wpad_vswitch / s130iom0_top_power_lvc_wpad |
| XIs130iom0_top_pwrdetv2 Is130iom0_top_pwrdetv2_in1_vddd_hv |
| + Is130iom0_top_pwrdetv2_in1_vddio_hv Is130iom0_top_pwrdetv2_in2_vddd_hv |
| + Is130iom0_top_pwrdetv2_in2_vddio_hv Is130iom0_top_pwrdetv2_in3_vddd_hv |
| + Is130iom0_top_pwrdetv2_in3_vddio_hv Is130iom0_top_pwrdetv2_out1_vddd_hv |
| + Is130iom0_top_pwrdetv2_out1_vddio_hv Is130iom0_top_pwrdetv2_out2_vddd_hv |
| + Is130iom0_top_pwrdetv2_out2_vddio_hv Is130iom0_top_pwrdetv2_out3_vddd_hv |
| + Is130iom0_top_pwrdetv2_out3_vddio_hv Is130iom0_top_pwrdetv2_rst_por_hv_n |
| + Is130iom0_top_pwrdetv2_tie_lo_esd Is130iom0_top_pwrdetv2_vccd |
| + Is130iom0_top_pwrdetv2_vddd1 Is130iom0_top_pwrdetv2_vddd2 |
| + Is130iom0_top_pwrdetv2_vddd_present_vddio_hv |
| + Is130iom0_top_pwrdetv2_vddio_present_vddd_hv Is130iom0_top_pwrdetv2_vddio_q |
| + Is130iom0_top_pwrdetv2_vssa Is130iom0_top_pwrdetv2_vssd |
| + Is130iom0_top_pwrdetv2_vssio_q / s130iom0_top_pwrdetv2 |
| XIs130iom0_top_tp1 Is130iom0_top_tp1_amuxbus_a Is130iom0_top_tp1_amuxbus_b |
| + Is130iom0_top_tp1_en_tp1 Is130iom0_top_tp1_tp1 Is130iom0_top_tp1_tp1_div |
| + Is130iom0_top_tp1_tp1_out Is130iom0_top_tp1_vccd Is130iom0_top_tp1_vcchib |
| + Is130iom0_top_tp1_vdda Is130iom0_top_tp1_vddio Is130iom0_top_tp1_vddio_q |
| + Is130iom0_top_tp1_vssa Is130iom0_top_tp1_vssd Is130iom0_top_tp1_vssio |
| + Is130iom0_top_tp1_vssio_q Is130iom0_top_tp1_vswitch / s130iom0_top_tp1 |
| XIs130iom0_top_tp2 Is130iom0_top_tp2_amuxbus_a Is130iom0_top_tp2_amuxbus_b |
| + Is130iom0_top_tp2_en_tp2 Is130iom0_top_tp2_tp2 Is130iom0_top_tp2_tp2_div |
| + Is130iom0_top_tp2_tp2_out Is130iom0_top_tp2_vccd Is130iom0_top_tp2_vcchib |
| + Is130iom0_top_tp2_vdda Is130iom0_top_tp2_vddio Is130iom0_top_tp2_vddio_q |
| + Is130iom0_top_tp2_vneg Is130iom0_top_tp2_vssa Is130iom0_top_tp2_vssd |
| + Is130iom0_top_tp2_vssio Is130iom0_top_tp2_vssio_q Is130iom0_top_tp2_vswitch |
| + / s130iom0_top_tp2 |
| XIs130iom0_top_tp3 Is130iom0_top_tp3_tp3 Is130iom0_top_tp3_tp3_out |
| + Is130iom0_top_tp3_vddd Is130iom0_top_tp3_vssd / s130iom0_top_tp3 |
| XIs130iom0_top_vrefcapv2 Is130iom0_top_vrefcapv2_amuxbus_a |
| + Is130iom0_top_vrefcapv2_amuxbus_b Is130iom0_top_vrefcapv2_cneg |
| + Is130iom0_top_vrefcapv2_cpos Is130iom0_top_vrefcapv2_vccd |
| + Is130iom0_top_vrefcapv2_vcchib Is130iom0_top_vrefcapv2_vdda |
| + Is130iom0_top_vrefcapv2_vddio Is130iom0_top_vrefcapv2_vddio_q |
| + Is130iom0_top_vrefcapv2_vssa Is130iom0_top_vrefcapv2_vssd |
| + Is130iom0_top_vrefcapv2_vssio Is130iom0_top_vrefcapv2_vssio_q |
| + Is130iom0_top_vrefcapv2_vswitch / s130iom0_top_vrefcapv2 |
| XIs130iom0_top_xres Is130iom0_top_xres_amuxbus_a Is130iom0_top_xres_amuxbus_b |
| + Is130iom0_top_xres_out Is130iom0_top_xres_out_h Is130iom0_top_xres_pad |
| + Is130iom0_top_xres_vccd Is130iom0_top_xres_vcchib Is130iom0_top_xres_vdda |
| + Is130iom0_top_xres_vddio Is130iom0_top_xres_vddio_q Is130iom0_top_xres_vssa |
| + Is130iom0_top_xres_vssd Is130iom0_top_xres_vssio Is130iom0_top_xres_vssio_q |
| + Is130iom0_top_xres_vswitch / s130iom0_top_xres |
| XIs130iom0_top_xres_2 Is130iom0_top_xres_2_amuxbus_a |
| + Is130iom0_top_xres_2_amuxbus_b Is130iom0_top_xres_2_out |
| + Is130iom0_top_xres_2_out_h Is130iom0_top_xres_2_pad |
| + Is130iom0_top_xres_2_vccd Is130iom0_top_xres_2_vcchib |
| + Is130iom0_top_xres_2_vdda Is130iom0_top_xres_2_vddio |
| + Is130iom0_top_xres_2_vddio_q Is130iom0_top_xres_2_vssa |
| + Is130iom0_top_xres_2_vssd Is130iom0_top_xres_2_vssio |
| + Is130iom0_top_xres_2_vssio_q Is130iom0_top_xres_2_vswitch / |
| + s130iom0_top_xres_2 |
| XIs130iom0_top_xres3v2 Is130iom0_top_xres3v2_amuxbus_a |
| + Is130iom0_top_xres3v2_amuxbus_b Is130iom0_top_xres3v2_pad |
| + Is130iom0_top_xres3v2_pad_a_esd_h Is130iom0_top_xres3v2_tie_weak_hi_h |
| + Is130iom0_top_xres3v2_vccd Is130iom0_top_xres3v2_vcchib |
| + Is130iom0_top_xres3v2_vdda Is130iom0_top_xres3v2_vddio |
| + Is130iom0_top_xres3v2_vddio_q Is130iom0_top_xres3v2_vssa |
| + Is130iom0_top_xres3v2_vssd Is130iom0_top_xres3v2_vssio |
| + Is130iom0_top_xres3v2_vssio_q Is130iom0_top_xres3v2_vswitch |
| + Is130iom0_top_xres3v2_xres_h_n Is130iom0_top_xres3v2_xres_n / |
| + s130iom0_top_xres3v2 |
| .ENDS |
| |
