s130/V2.1.1/DIG/scs130ls/V0.0.0/verilog/scs130ls_lpflow_srsdfxtp2_4.v

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Wed Aug 31 15:45:58 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`timescale
// `ifndef dont_change_delay_mode;`endif\n
// `ifndef dont_change_delay_mode;`else\n
// `ifndef dont_change_delay_mode;`endif\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 25 14:47:58 EDT 2011

`celldefine


`timescale 1ns / 1ps

module scs130ls_lpflow_srsdfxtp2_4  (

output Q,
input CLK,
input D,
input SCD,
input SCE,
input SLEEPB

`ifdef SC_USE_PG_PIN
,
input kapwr,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);



wire buf_Q;
wire mux_out;
`ifdef TETRAMAX
  wire clk_slpn;
  and (clk_slpn, CLK, SLEEPB);
  scs130ls_lpflow_pg_U_MUX_2_1 (mux_out,D,SCD,SCE);
  scs130ls_lpflow_pg_U_DF_P ( buf_Q , mux_out , clk_slpn ) ;
  buf(Q, buf_Q) ;
`else

  `ifdef SC_USE_PG_PIN
  `else
  supply1 kapwr;
  supply1 vpwr;
  supply0 vgnd;
  supply1 vpb;
  supply0 vnb;
  `endif


  `ifdef functional
    scs130ls_lpflow_pg_U_MUX_2_1 (mux_out,D,SCD,SCE);
    scs130ls_lpflow_pg_U_DF_P_NO_SLEEPB_pg #0.001 ( buf_Q , mux_out , CLK , SLEEPB ,  , kapwr , vgnd , vpwr ) ;
  `else
    reg notifier;
    wire D_delayed;
    wire SCD_delayed;
    wire SCE_delayed;
    wire CLK_delayed;
    scs130ls_lpflow_pg_U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed);
    scs130ls_lpflow_pg_U_DF_P_NO_SLEEPB_pg ( buf_Q , mux_out , CLK_delayed, SLEEPB_delayed , notifier , kapwr , vgnd , vpwr ) ;

    wire AWAKE;
    wire COND1;
    wire COND2;
    wire COND3;
    assign AWAKE = (SLEEPB_delayed === 1'b1);
    assign COND1 = ((SCE_delayed === 1'b0) && AWAKE);
    assign COND2 = ((SCE_delayed === 1'b1) && AWAKE);
    assign COND3 = ((D_delayed !== SCD_delayed) && AWAKE);
    specify
      (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
      $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
      $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
      $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
      $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
      $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
      $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
      $width (posedge CLK &&& AWAKE , 0:0:0 , 0, notifier);
      $width (negedge CLK &&& AWAKE , 0:0:0 , 0, notifier);

  //  insure clean entry into and exit from sleep mode
      $setuphold  ( negedge CLK , posedge SLEEPB , 0:0:0 , 0:0:0, notifier , , , CLK_delayed, SLEEPB_delayed) ;
      $setuphold  ( posedge CLK , negedge SLEEPB , 0:0:0 , 0:0:0, notifier , , , CLK_delayed, SLEEPB_delayed) ;
      $setuphold  ( posedge CLK , posedge SLEEPB , 0:0:0 , 0:0:0, notifier , , , CLK_delayed, SLEEPB_delayed) ;
  // this is required for an arc that is always zero in old characterization data
      $setuphold  ( negedge CLK,  negedge SLEEPB , 0:0:0 , 0:0:0, notifier , , , CLK_delayed, SLEEPB_delayed) ;

    endspecify
  `endif
 
 
 scs130ls_lpflow_pg_U_VPWR_VGND (UDP_OUT_Q, buf_Q, vpwr, vgnd) ;
 buf(Q, UDP_OUT_Q) ;
`endif

endmodule
`endcelldefine