s130/V2.1.1/DIG/scs130hvl/V0.0.0/verilog/scs130hvl_pg_U_isosrchvaon.v

primitive scs130hvl_pg_U_isosrchvaon ( UDP_OUT, UDP_IN, VPWR, LVPWR, VGND, SLEEP);
  output UDP_OUT;
  input UDP_IN, VPWR, LVPWR, VGND, SLEEP;

  table
//   in  VPWR LVPWR VGND  SLEEP   : out
      0    1    1     0     b     : 0 ;
      1    1    1     0     0     : 1 ;
      b    1    ?     0     1     : 0 ;
      ?    1    0     0     1     : 0 ;

      // Explicitly listing this case since it may not be obvious.
      // Output of cell would be 0, but making it x since there
      // would be large power consumption
      x    1    1     0     1     : x ;

  endtable
endprimitive