s130/V2.1.1/DIG/scs130hvl/V0.0.0/verilog/scs130hvl_o22a_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:32 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:12 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps


module scs130hvl_o22a_1  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif

`endif

  wire csi_opt_294;
  wire csi_opt_292;

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
    if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0);
    if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
    if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0);
    if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  or ( csi_opt_292 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs130hvl_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf   (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine