s130/V2.1.1/DIG/scs130hvl/V0.0.0/verilog/scs130hvl_lsbuflv2hv_isosrchvaon_1.v

// 04/19/13 Merged scs130hvl_lsbuflv2hv_1 and scs8ls_lpflow_isobufsrc_1.v

`celldefine
`timescale 1ns / 1ps


module scs130hvl_lsbuflv2hv_isosrchvaon_1  (
output X,
input A,
input SLEEPB


`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input lvpwr,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 lvpwr;
supply1 vpb;
supply0 vnb;
`endif
`endif

wire SLEEP ;

`ifdef functional
`else

	specify
    (SLEEPB +=> X) = (0:0:0,0:0:0);
    (A +=> X) = (0:0:0,0:0:0);
	endspecify
`endif

not (SLEEP, SLEEPB) ;
and (UDP_IN_X, SLEEPB, A) ;
`ifdef SC_USE_PG_PIN
  scs130hvl_pg_U_isosrchvaon (UDP_OUT_X, UDP_IN_X, vpwr, lvpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
`else
  buf ( X , UDP_IN_X ) ;
`endif
endmodule
`endcelldefine