s130/V2.1.1/DIG/scs130hvl/V0.0.0/verilog/scs130hvl_dlxtp_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:32 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:12 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps



module scs130hvl_dlxtp_1  (
output Q,

input D,
input GATE

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif

`endif

  `ifdef functional
    `ifdef SC_USE_PG_PIN
      scs130hvl_pg_U_DL_P_NO_pg  #0.001 ( buf_Q , D , GATE , , vpwr , vgnd ) ;
    `else
      scs130hvl_pg_U_DL_P  #0.001 ( buf_Q , D , GATE ) ;
    `endif
  `else
    reg notifier;
  wire buf_Q;
  wire GATE_delayed;
  wire D_delayed;
  scs130hvl_pg_U_DL_P_NO_pg (  buf_Q , D_delayed , GATE_delayed , notifier , vpwr , vgnd  ) ;
    specify
      (D +=> Q ) = (0:0:0,0:0:0);  // delays are tris,tfall
      
      (posedge GATE => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall
      
      $width (posedge GATE , 0:0:0, 0, notifier);
      
      $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ;
      $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , , GATE_delayed , D_delayed ) ;
    endspecify
  `endif
  `ifdef SC_USE_PG_PIN



  buf (UDP_IN_Q,buf_Q);
  scs130hvl_pg_U_VPWR_VGND (Q, UDP_IN_Q, vpwr, vgnd) ;

  `else
    buf ( Q , buf_Q ) ;
  `endif
endmodule
`endcelldefine