s130/V2.1.1/DIG/scs130hvl/V0.0.0/lib/scs130hvl_diode.lib

 library (scs130hvl_diode) {
  technology (cmos) ;
  delay_model : table_lookup ;
  capacitive_load_unit (1,pf) ;
  pulling_resistance_unit : "1kohm" ;
  time_unit : "1ns" ;
  voltage_unit : "1V" ;
  current_unit : "1mA" ;
  leakage_power_unit : "1nW" ;
  default_fanout_load : 0.0 ;
  default_inout_pin_cap : 0.0 ;
  default_input_pin_cap : 0.0 ;
  default_output_pin_cap : 0.0 ;
  default_cell_leakage_power : 0.000000;
  default_leakage_power_density : 0.000000;
  input_threshold_pct_rise : 50.0 ;
  input_threshold_pct_fall : 50.0 ;
  output_threshold_pct_rise : 50.0 ;
  output_threshold_pct_fall : 50.0 ;
  slew_lower_threshold_pct_fall : 20.0 ;
  slew_lower_threshold_pct_rise : 20.0 ;
  slew_upper_threshold_pct_fall : 80.0 ;
  slew_upper_threshold_pct_rise : 80.0 ;

/* adding contents of sps_ext_lib_head.txt */  revision : 1.000000 ;
  bus_naming_style : "%s[%d]" ;
  simulation : true ;
  nom_process : 1.0 ;
  nom_temperature : -40 ;
  nom_voltage : 5.5 ;
  in_place_swap_mode : match_footprint ;
  default_max_transition : 3.75 ;

  /* operation conditions */
  operating_conditions("max") {
    process     : 1 ;
    temperature : -40 ;
    voltage     : 5.5 ;
    tree_type   : balanced_tree ;
  }

  default_operating_conditions : "max" ;

  voltage_map(vpwr, 5.5) ;
  voltage_map(vpb, 5.5) ;
  voltage_map(vgnd, 0.0) ;
  voltage_map(vnb, 0.0) ;

cell (scs130hvl_diode_2) { 
  pg_pin (vpb) {
    voltage_name : vpb ;
    pg_type : "nwell";
  }
  pg_pin (vnb) {
    voltage_name : vnb ;
    pg_type : "pwell";
  }
  pg_pin (vpwr) {
    voltage_name : vpwr ;
    pg_type : primary_power ;
  }
  pg_pin (vgnd) {
    voltage_name : vgnd ;
    pg_type : primary_ground ;
  }
  dont_touch : true;
  dont_use : true;
  area : 3.9072;
  pin(DIODE) {
    max_transition : 3.75 ;
    related_power_pin : vpwr ;
    related_ground_pin : vgnd ;
    direction : input;
    capacitance : 0.0013122;
    clock : false ;
  }
  cell_leakage_power : "0.001375" ;
}

}