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// Automatically modified by replacePGwithIfDef.pl
// iptguser Thu Aug 18 13:10:23 EDT 2011
// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser Mon Aug 8 14:40:05 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults
`celldefine
`timescale 1ns / 1ps
module scs8lp_srsdfstp_1 (
output Q,
input CLK,
input D,
input SCD,
input SCE,
input SETB,
input SLEEPB
`ifdef SC_USE_PG_PIN
, input kapwr
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
wire set;
wire mux_out;
`ifdef TETRAMAX
wire clk_slpn;
wire slp;
and (clk_slpn, CLK, SLEEPB);
not (slp, SLEEPB);
nor (set,SETB, slp);
scs8lpa_U_MUX_2_1 (mux_out,D,SCD,SCE);
scs8lpa_U_DF_P_S ( Q , mux_out , clk_slpn , set ) ;
`else
`ifdef SC_USE_PG_PIN
`else
supply1 kapwr;
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
wire buf_Q;
`ifdef functional
not (set,SETB);
scs8lpa_U_MUX_2_1 (mux_out,D,SCD,SCE);
scs8lpa_U_DF_P_S_NO_SLEEPB_pg #0.001 ( buf_Q , mux_out , CLK , set, SLEEPB , , kapwr , vgnd , vpwr ) ;
`else
reg notifier;
wire D_delayed;
wire SCD_delayed;
wire SCE_delayed;
wire SETB_delayed;
wire CLK_delayed;
not (set,SETB_delayed);
scs8lpa_U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed);
scs8lpa_U_DF_P_S_NO_SLEEPB_pg ( buf_Q , mux_out , CLK_delayed , set, SLEEPB , notifier , kapwr , vgnd , vpwr ) ;
wire AWAKE;
wire COND0;
wire COND1;
wire COND2;
wire COND3;
wire COND4;
assign AWAKE = ((SLEEPB === 1'b1) && AWAKE);
assign COND0 = ((SETB_delayed === 1'b1) && AWAKE);
assign COND1 = ((SCE_delayed === 1'b0) && COND0 && AWAKE);
assign COND2 = ((SCE_delayed === 1'b1) && COND0 && AWAKE);
assign COND3 = ((D_delayed !== SCD_delayed) && COND0 && AWAKE);
assign COND4 = ((SETB === 1'b1) && AWAKE);
specify
(negedge SETB => (Q -: SETB ) ) = 0:0:0; // delay is tris
(posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
$recrem ( posedge SETB , posedge CLK , 0:0:0, 0:0:0, notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
$width (posedge CLK &&& COND4 , 1.0:1.0:1.0, 0, notifier);
$width (negedge CLK &&& COND4 , 1.0:1.0:1.0, 0, notifier);
$width (negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
$width (posedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
endspecify
`endif
scs8lpa_U_VPWR_VGND (UDP_OUT_Q, buf_Q, vpwr, vgnd) ;
buf(Q, UDP_OUT_Q) ;
`endif
endmodule
`endcelldefine