scs8lp/V0.0.1/verilog/scs8lp_iso0p_lp.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:18 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:01 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps
module scs8lp_iso0p_lp  (
output X,
input A,
input sleep

`ifdef SC_USE_PG_PIN
, input kapwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 kapwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  
  wire sleepn;

`ifdef functional
`else
	specify
    (A +=> X) = (0:0:0,0:0:0);
    (sleep -=> X) = (0:0:0,0:0:0);
	endspecify

`endif

  not ( sleepn ,  sleep );
  `ifdef SC_USE_PG_PIN

  scs8lpa_U_VPWR_VGND (UDP_OUT_A, A, kapwr, vgnd) ;
  scs8lpa_U_VPWR_VGND (UDP_OUT_sleepn, sleepn, kapwr, vgnd) ;
  and  ( X ,  UDP_OUT_A , UDP_OUT_sleepn );

  `else
    and ( X , A , sleepn ) ;
  `endif
endmodule
`endcelldefine