scs8lp/V0.0.1/verilog/scs8lp_dlxtn_2.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:17 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:00 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps

module scs8lp_dlxtn_2  (
output Q,

input D,
input GATEN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif



  wire gate;
  wire buf_Q;
  wire GATEN_delayed;
  wire D_delayed;

`ifdef functional
`ifdef SC_USE_PG_PIN
 scs8lpa_U_DL_P_NO_pg #0.001 ( buf_Q , D , gate ,  , vpwr , vgnd ) ;
`else
 scs8lpa_U_DL_P #0.001 ( buf_Q , D , gate ) ;
`endif
    not(gate, GATEN);
`else
    reg notifier;
scs8lpa_U_DL_P_NO_pg  ( buf_Q , D_delayed , gate , notifier , vpwr , vgnd ) ;
    not (gate,GATEN_delayed);
`endif

  buf (Q,buf_Q);

`ifdef functional
`else
	specify
		(D +=> Q ) = (0:0:0,0:0:0);  // delays are tris,tfall
    
		(negedge GATEN => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall
    
		$width (posedge GATEN , 0:0:0, 0, notifier);
		$width (negedge GATEN , 0:0:0, 0, notifier);
    
    $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ;
    $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , , GATEN_delayed , D_delayed ) ;
	endspecify
`endif

endmodule
`endcelldefine