blob: 82865e68ae538038c99d86fbbb91522e47eb4904 [file] [log] [blame]
// Automatically modified by replacePGwithIfDef.pl
// iptguser Thu Aug 18 13:10:15 EDT 2011
// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser Mon Aug 8 14:40:00 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults
`celldefine
`timescale 1ns / 1ps
module scs8lp_bushold0_1 (
inout X,
input RESET
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
wire xb;
`ifdef SC_USE_PG_PIN
scs8lpa_U_VPWR_VGND (UDP_OUT_X, X, vpwr, vgnd);
scs8lpa_U_VPWR_VGND (UDP_OUT_RESET, RESET, vpwr, vgnd);
not (xb,UDP_OUT_X);
nor (weak0,weak1) (X,xb,UDP_OUT_RESET);
`else
not ( xb , X ) ;
nor (weak0,weak1) (X,xb,RESET);
`endif
`ifdef functional
`else
specify
if ((X)) ( RESET -=> X ) = (0:0:0); // delays are tris
endspecify
`endif
endmodule
`endcelldefine