scs8lp/V0.0.0/verilog/scs8lp_srsdfrtn_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:23 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:05 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps

module scs8lp_srsdfrtn_1  (
output Q,
input CLKN,
input D,
input SCD,
input SCE,
input RESETB,
input SLEEPB

`ifdef SC_USE_PG_PIN
, input kapwr
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 kapwr;
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not (reset,RESETB);
  scs8lpa_U_MUX_2_1 (mux_out,D,SCD,SCE);
  scs8lpa_U_DF_N_R_SLEEPB_pg #0.001 ( buf_Q , mux_out , CLKN , reset , SLEEPB , kapwr , vgnd , vpwr ) ;
`else
  reg notifier;
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLKN_delayed;
  not (reset,RESETB_delayed);
  scs8lpa_U_MUX_2_1 (mux_out,D_delayed,SCD_delayed,SCE_delayed);
  scs8lpa_U_DF_N_R_NO_SLEEPB_pg #0.001 ( buf_Q , mux_out , CLKN_delayed , reset, SLEEPB , notifier , kapwr , vgnd , vpwr ) ;

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ((SLEEPB === 1'b1) && AWAKE);
  assign COND0 = ((RESETB_delayed === 1'b1) && AWAKE);
  assign COND1 = ((SCE_delayed === 1'b0) && COND0 && AWAKE);
  assign COND2 = ((SCE_delayed === 1'b1) && COND0 && AWAKE);
  assign COND3 = ((D_delayed !== SCD_delayed) && COND0 && AWAKE);
  assign COND4 = ((RESETB === 1'b1) && AWAKE);
  specify
    (negedge RESETB => (Q +: RESETB ) ) = 0:0:0;  // delay is tris
    (negedge CLKN => (Q : CLKN ) ) = (0:0:0,0:0:0); // delays are tris,tfall
    $recrem ( posedge RESETB , negedge CLKN , 0:0:0, 0:0:0, notifier , AWAKE , AWAKE , RESETB_delayed , CLKN_delayed ) ;
    $setuphold ( negedge CLKN , posedge D , 0:0:0, 0:0:0, notifier , COND1 , COND1 , CLKN_delayed , D_delayed ) ;
    $setuphold ( negedge CLKN , negedge D , 0:0:0, 0:0:0, notifier , COND1 , COND1 , CLKN_delayed , D_delayed ) ;
    $setuphold ( negedge CLKN , posedge SCD , 0:0:0, 0:0:0, notifier , COND2 , COND2 , CLKN_delayed , SCD_delayed ) ;
    $setuphold ( negedge CLKN , negedge SCD , 0:0:0, 0:0:0, notifier , COND2 , COND2 , CLKN_delayed , SCD_delayed ) ;
    $setuphold ( negedge CLKN , posedge SCE , 0:0:0, 0:0:0, notifier , COND3 , COND3 , CLKN_delayed , SCE_delayed ) ;
    $setuphold ( negedge CLKN , negedge SCE , 0:0:0, 0:0:0, notifier , COND3 , COND3 , CLKN_delayed , SCE_delayed ) ;
    $width (posedge CLKN &&& COND4 , 1.0:1.0:1.0, 0, notifier);
    $width (negedge CLKN &&& COND4 , 1.0:1.0:1.0, 0, notifier);
    $width (negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
    $width (posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
  endspecify
`endif

  bufif1 ( Q , buf_Q , vpwr );

endmodule
`endcelldefine