scs8lp/V0.0.0/verilog/scs8lp_srdlrtp_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:23 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:05 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps

module scs8lp_srdlrtp_1  (
output Q,
input RESETB,
input D,
input GATE,
input SLEEPB

`ifdef SC_USE_PG_PIN
, input kapwr
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 kapwr;
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;

`ifdef functional
  not (reset,RESETB);
  scs8lpa_U_DL_P_R_SLEEPB_pg #0.001 ( buf_Q , D , GATE , reset , SLEEPB , kapwr , vgnd , vpwr ) ;
`else
  reg notifier;
  wire D_delayed;
  wire GATE_delayed;
  wire RESET_delayed;
  not (reset,RESETB_delayed);
  scs8lpa_U_DL_P_R_NO_SLEEPB_pg ( buf_Q , D_delayed , GATE_delayed , reset, SLEEPB , notifier , kapwr , vgnd , vpwr ) ;

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = (SLEEPB === 1'b1);
  assign COND0 = (AWAKE && (RESETB_delayed === 1'b1));
  assign COND1 = (AWAKE && (RESETB === 1'b1));
  specify
    if ((!GATE)) (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0);  // delay is tfall
    ifnone ( RESETB +=> Q )  = (0:0:0,0:0:0);
    (D +=> Q ) = (0:0:0,0:0:0);  // delays are tris,tfall
    (posedge GATE => (Q +: D ) ) = (0:0:0,0:0:0); // delays are tris,tfall

    $width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0, notifier);
    $width ( negedge GATE &&& COND1 , 1.0:1.0:1.0 , 0, notifier);
    $recrem ( posedge RESETB , negedge GATE , 0:0:0, 0:0:0, notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ;
    $setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
    $setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier);
  endspecify
`endif

  bufif1 ( Q , buf_Q , vpwr );

endmodule
`endcelldefine