scs8lp/V0.0.0/verilog/scs8lp_fahcin_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:17 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:00 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults


`celldefine
`timescale 1ns / 1ps
module scs8lp_fahcin_1  (
output COUT,
output SUM,
input A,
input B,
input CIN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0);
    if ((B&CIN)) (A +=> COUT) = (0:0:0,0:0:0);
    if ((!A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0);
    if ((A&CIN)) (B +=> COUT) = (0:0:0,0:0:0);
    if ((!A&B)) (CIN -=> COUT) = (0:0:0,0:0:0);
    if ((A&!B)) (CIN -=> COUT) = (0:0:0,0:0:0);
    if ((!B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0);
    if ((!B&CIN)) (A +=> SUM) = (0:0:0,0:0:0);
    if ((B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0);
    if ((B&CIN)) (A -=> SUM) = (0:0:0,0:0:0);
    if ((!A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0);
    if ((!A&CIN)) (B +=> SUM) = (0:0:0,0:0:0);
    if ((A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0);
    if ((A&CIN)) (B -=> SUM) = (0:0:0,0:0:0);
    if ((!A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0);
    if ((!A&B)) (CIN +=> SUM) = (0:0:0,0:0:0);
    if ((A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0);
    if ((A&B)) (CIN -=> SUM) = (0:0:0,0:0:0);
	endspecify
`endif

  not(CI,CIN);
  xor (UDP_IN_SUM,A,B,CI);
  `ifdef SC_USE_PG_PIN

  scs8lpa_U_VPWR_VGND (UDP_OUT_SUM, UDP_IN_SUM, vpwr, vgnd) ;
  buf   (SUM, UDP_OUT_SUM) ;

  `else
    buf ( SUM , UDP_IN_SUM ) ;
  `endif
  and (A$B,A,B),(A$CI,A,CI),(B$CI,B,CI);
  or (UDP_IN_COUT,A$B,A$CI,B$CI);
  `ifdef SC_USE_PG_PIN
  scs8lpa_U_VPWR_VGND (UDP_OUT_COUT, UDP_IN_COUT, vpwr, vgnd) ;
  buf   (COUT, UDP_OUT_COUT) ;
  `else
  buf   (COUT, UDP_IN_COUT) ;
  `endif

endmodule
`endcelldefine