scs8lp/V0.0.0/verilog/scs8lp_dlrtn_4.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:17 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:00 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps

module scs8lp_dlrtn_4  (
output Q,

input RESETB,
input D,
input GATEN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire reset;
  wire intgate;

`ifdef functional
  not (reset,RESETB);
  not (intgate,GATEN);
`ifdef SC_USE_PG_PIN
 scs8lpa_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , intgate , reset ,  , vpwr , vgnd ) ;
`else
 scs8lpa_U_DL_P_R #0.001 ( buf_Q , D , intgate , reset ) ;
`endif
`else
  reg notifier;
  wire COND0;
  wire D_delayed;
  wire GATEN_delayed;
  wire RESET_delayed;
  not (reset,RESETB_delayed);
  not (intgate,GATEN_delayed);
scs8lpa_U_DL_P_R_NO_pg  ( buf_Q , D_delayed , intgate , reset , notifier , vpwr , vgnd ) ;

  assign COND0 = (RESETB_delayed === 1'b1);
  specify
    (negedge RESETB => (Q +: RESETB ) ) = (0:0:0,0:0:0);  // delay is tfall
    (D +=> Q ) = (0:0:0,0:0:0);  // delays are tris,tfall
    (negedge GATEN => (Q : GATEN ) ) = (0:0:0,0:0:0); // delays are tris,tfall

    $width (posedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier);
    $width (negedge GATEN &&& (RESETB===1'b1) , 0:0:0, 0, notifier);
    $recrem ( posedge RESETB , posedge GATEN , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , GATEN_delayed ) ;
    $setuphold ( posedge GATEN , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ;
    $setuphold ( posedge GATEN , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATEN_delayed , D_delayed ) ;
  endspecify
`endif

buf (Q,buf_Q);

endmodule
`endcelldefine