scs8hvl/V0.0.2/verilog/scs8hvl_pg_U_VPWR_VGND.v

primitive scs8hvl_pg_U_VPWR_VGND ( UDP_OUT, UDP_IN, VPWR, VGND);
  output UDP_OUT;
  input UDP_IN, VPWR, VGND;

// UDP_OUT:=x when VPWR!=1 or VGND!=0
// UDP_OUT:=UDP_IN when VPWR==1 and VGND==0

  table
//  X_int VPWR VGND : X
      0    1    0   : 0 ;
      1    1    0   : 1 ;
      1    0    0   : x ;
      1    1    1   : x ;
      1    x    0   : x ;
      1    1    x   : x ;
  endtable
endprimitive