scs8hvl/V0.0.0/verilog/scs8hvl_lsbufhv2hv_hl_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:32 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:12 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps


module scs8hvl_lsbufhv2hv_hl_1  (
output X,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input lowhvpwr,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 lowhvpwr;
supply1 vpb;
supply0 vnb;
`endif

`endif

`ifdef functional
`else
reg csi_notifier;

	specify
    (A +=> X) = (0:0:0,0:0:0);
	endspecify
`endif
  `ifdef SC_USE_PG_PIN
    scs8hvl_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
    buf  (UDP_OUT_X, UDP_OUT_A) ;
    scs8hvl_pg_U_VPWR_VGND  (X, UDP_OUT_X, lowhvpwr, vgnd) ;
  `else
    buf ( X , A ) ;
  `endif
endmodule
`endcelldefine