scs8hvl/V0.0.0/verilog/scs8hvl_einvp_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:32 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:12 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps



module scs8hvl_einvp_1  (
output Z,

input A,
input TE

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif

`endif



`ifdef SC_USE_PG_PIN
  scs8hvl_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hvl_pg_U_VPWR_VGND (UDP_OUT_TE, TE, vpwr, vgnd) ;
  notif1 (Z,UDP_OUT_A,UDP_OUT_TE);
`else
  notif1 (Z,A,TE);
`endif

`ifdef functional
`else
	specify
		if (TE ) (A -=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
		(TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
	endspecify
`endif

endmodule
`endcelldefine