scs8hvl/V0.0.0/verilog/scs8hvl_dfxbp_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:32 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:12 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps



module scs8hvl_dfxbp_1  (
output Q,
output QN,

input CLK,
input D

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif

`endif

  wire buf_Q;

`ifdef functional
  `ifdef SC_USE_PG_PIN
    scs8hvl_pg_U_DF_P_NO_pg  #0.001 ( buf_Q , D , CLK , , vpwr , vgnd ) ;
  `else
    scs8hvl_pg_U_DF_P  #0.001 ( buf_Q , D , CLK ) ;
  `endif
`else
  reg notifier;
  wire D_delayed;
  wire CLK_delayed;
  scs8hvl_pg_U_DF_P_NO_pg (  buf_Q , D_delayed , CLK_delayed , notifier , vpwr , vgnd  ) ;
  specify
    (posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
    (posedge CLK => (QN : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
    $width (posedge CLK , 0:0:0, 0, notifier);
    $width (negedge CLK , 0:0:0, 0, notifier);
    $setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ;
    $setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , , CLK_delayed , D_delayed ) ;
  endspecify
`endif
  `ifdef SC_USE_PG_PIN


buf (UDP_IN_Q,buf_Q);
  scs8hvl_pg_U_VPWR_VGND (Q, UDP_IN_Q, vpwr, vgnd) ;
not (UDP_IN_QN,buf_Q);
  scs8hvl_pg_U_VPWR_VGND (QN, UDP_IN_QN, vpwr, vgnd) ;

  `else
    buf ( Q , buf_Q ) ;
    not ( QN , buf_Q ) ;
  `endif
endmodule
`endcelldefine