scs8hvl/V0.0.0/verilog/scs8hvl_a21oi_1.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Fri Aug 12 15:57:31 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Fri Aug 12 15:57:11 EDT 2011
// `suppress_faults;`enable_portfaults\n
// `ifdef TETRAMAX;`endif\n
// `ifdef functional;`endif\n
// `ifndef dont;`endif\n
// `else;`delay_mode_path\n
// `endif;\n
// `disable_portfaults;`nosuppress_faults\n

`celldefine
`timescale 1ns / 1ps


module scs8hvl_a21oi_1  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif

`endif

  wire csi_opt_273;

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
reg csi_notifier;

	specify
    (A1 -=> Y) = (0:0:0,0:0:0);
    (A2 -=> Y) = (0:0:0,0:0:0);
    if ((!A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0);
    if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0);
    if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0);
	endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hvl_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf   (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine