| when(simSimulator=="auCdl" | |
| when( "$PDK_HOME/../../s8rr/V2.0.1/LVS/Calibre/source.cdl" | |
| incFILE = "$PDK_HOME/../../s8rr/V2.0.1/LVS/Calibre/source.cdl" | |
| auCdlSkipMEGA = 't | |
| );when | |
| ; needed for netlisting hrpoly & uhrpoly resistors | |
| simrcRes = strcat( getShellEnvVar("PDK_HOME") "/VirtuosoOA/SKILL/dev/pcells/simrc.resPcell" ) | |
| when( simrcRes | |
| load(simrcRes) | |
| );when | |
| );when | |