| `timescale 1ns/1ps |
| module s8fmlt_32k_top_atpg (vpwr, vpb, vnb, vgnd, |
| iso,reset,clk, |
| scan_en,scan_mode,scanb_mp_tm,scanb_tm_dpg, |
| scan_in1,scan_out1,scan_in2,scan_out2, |
| mode,seq,ca,ra,axa,di,pa,pw, |
| dout |
| ); |
| input vpwr, vpb, vnb, vgnd; |
| input iso,reset,clk,scan_en,scan_in1,scan_in2,scan_mode,scanb_tm_dpg; |
| input axa; |
| input [8:0] ra; |
| input [3:0] ca; |
| input pw; |
| input [6:0] pa; |
| input [7:0] di; |
| input [1:0] seq; |
| input [3:0] mode; |
| output scan_out1,scan_out2; |
| output [63:0] dout; |
| output scanb_mp_tm; |
| |
| s8fmlt_32k_nsw_atpg fm32k_nsw(.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), |
| .iso(iso),.reset(reset),.clk(clk), |
| .scan_en(scan_en),.scan_mode(scan_mode),.scanb_mp_tm(scanb_mp_tm), .scanb_tm_dpg(scanb_tm_dpg), |
| .scan_in1(scan_in1),.scan_out1(scan_out1),.scan_in2(scan_in2),.scan_out2(scan_out2), |
| .mode(mode),.seq(seq),.ca(ca),.ra(ra),.axa(axa),.di(di),.pa(pa),.pw(pw), |
| .dout(dout) |
| ); |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_32k_nsw_atpg (vpwr, vpb, vnb, vgnd, |
| iso,reset,clk, |
| scan_en,scan_mode,scanb_mp_tm,scanb_tm_dpg, |
| scan_in1,scan_out1,scan_in2,scan_out2, |
| mode,seq,ca,ra,axa,di,pa,pw, |
| dout |
| ); |
| input vpwr, vpb, vnb, vgnd; |
| |
| input iso,reset,clk,scan_en,scan_in1,scan_in2,scan_mode,scanb_tm_dpg; |
| input axa; |
| input [8:0] ra; |
| input [3:0] ca; |
| input pw; |
| input [6:0] pa; |
| input [7:0] di; |
| input [1:0] seq; |
| input [3:0] mode; |
| output [63:0] dout; |
| output scan_out1,scan_out2; |
| output scanb_mp_tm; |
| |
| wire scanb_dpg_prd,scan_prd_sa,scanb_mp_tm,scan_sa_mp; |
| wire resetb; |
| |
| not I1 (resetb,reset); |
| |
| s8fmlt_predec_atpg predec (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .ra(ra), .clk(clk), .ca(ca),.reset(reset), |
| .axa(axa), .scan_en(scan_en), .scan_inb(scanb_dpg_prd), .scan_out(scan_out1),.iso(iso)); |
| |
| s8fmlt_dinpg_atpg dinpg (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .pa(pa),.clk(clk),.scan_mode(scan_mode), .scan_outb(scanb_dpg_prd), .reset(reset), |
| .scan_en(scan_en), .scan_inb(scanb_tm_dpg), .pw(pw), .di(di)); |
| |
| s8fmlt_spine16x64_atpg spine16x64 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .clk(clk), .scan_mode(scan_mode), .scan_in(scan_in2), .scan_out(scan_sa_mp), .dout(dout[63:0]), .iso(iso), |
| .resetb(resetb)); |
| |
| s8fmlt_mpcont_atpg mpcont (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .axa(axa),.clk(clk),.iso(iso), |
| .scan_mode(scan_mode), .scan_in(scan_in1), .scan_sa_mp(scan_sa_mp),.scan_en(scan_en), .mode(mode),.scanb_mp_tm(scanb_mp_tm),.scan_out(scan_out2), |
| .seq(seq), .reset(reset)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_predec_atpg (vpwr, vpb, vnb, vgnd, scan_out, axa, ca, |
| clk, ra, reset, scan_en, scan_inb, iso ); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| |
| input axa, clk, reset, scan_en, scan_inb,iso; |
| |
| input [3:0] ca; |
| input [8:0] ra; |
| |
| wire scanb_cpre_rpre; |
| |
| s8fmlt_cpre_atpg cpren (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_outb(scanb_cpre_rpre), .scan_inb(scan_inb), .ca({1'b0, 1'b0, ca}), .reset(reset), .scan_en(scan_en), |
| .aclkw(clk)); |
| s8fmlt_rpre_atpg rpre (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_inb(scanb_cpre_rpre), .ba_3(1'b0), .ra(ra[8:0]), .scan_out(scan_out), .scan_en(scan_en), |
| .reset(reset), .axa(axa), .aclkw(clk),.iso(iso)); |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_cpre_atpg (vpwr, vpb, vnb, vgnd, scan_outb, aclkw, ca, reset, scan_en, scan_inb); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb; |
| |
| input aclkw, reset, scan_en, scan_inb; |
| |
| input [5:0] ca; |
| |
| wire [5:0] calb; |
| wire [5:0] cal; |
| |
| |
| not I44 ( scan_outb, net109); |
| not I46 ( net109, calb[5]); |
| not I456 ( resetb, reset); |
| s8fmlt_dffsc cadlat5 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(calb[4]), .SC_EN(scan_en), .CD(resetb), .QN(calb[5]), .Q(cal[5]), .D(ca[5]), .CP(aclkw) ); |
| s8fmlt_dffsc cadlat0 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(scan_inb), .SC_EN(scan_en), .CD(resetb), .QN(calb[0]), .Q(cal[0]), .D(ca[0]), .CP(aclkw) ); |
| s8fmlt_dffsc cadlat3 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(calb[2]), .SC_EN(scan_en), .CD(resetb), .QN(calb[3]), .Q(cal[3]), .D(ca[3]), .CP(aclkw) ); |
| s8fmlt_dffsc cadlat1 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(calb[0]), .SC_EN(scan_en), .CD(resetb), .QN(calb[1]), .Q(cal[1]), .D(ca[1]), .CP(aclkw) ); |
| s8fmlt_dffsc cadlat2 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(calb[1]), .SC_EN(scan_en), .CD(resetb), .QN(calb[2]), .Q(cal[2]), .D(ca[2]), .CP(aclkw) ); |
| s8fmlt_dffsc cadlat4 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(calb[3]), .SC_EN(scan_en), .CD(resetb), .QN(calb[4]), .Q(cal[4]), .D(ca[4]), .CP(aclkw) ); |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_rpre_atpg (vpwr, vpb, vnb, vgnd, scan_out, aclkw, axa, ba_3, ra, reset, scan_en, scan_inb, iso); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| input aclkw, axa, ba_3, reset, scan_en, scan_inb, iso; |
| |
| |
| input [8:0] ra; |
| |
| wire [8:0] ralb; |
| |
| wire [8:0] ral; |
| |
| // Buses in the design |
| |
| wire [3:3] balb; |
| |
| wire [3:3] bal; |
| |
| wire net60,net66,resetb; |
| |
| not I198 ( net60, balb[3]); |
| not I46 ( net66, net60); |
| not ( strong0,strong1 ) I151 ( resetb, reset); |
| nor I130 ( scan_out, iso, net66); |
| s8fmlt_dffsc raddlat_10_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(axalb), .SC_EN(scan_en), .CD(resetb), .QN(balb[3]), .Q(bal[3]), .D(ba_3), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_9_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[8]), .SC_EN(scan_en), .CD(resetb), .QN(axalb), .Q(axal), .D(axa), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_8_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[7]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[8]), .Q(ral[8]), .D(ra[8]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_7_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[6]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[7]), .Q(ral[7]), .D(ra[7]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_6_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[5]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[6]), .Q(ral[6]), .D(ra[6]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_5_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[4]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[5]), .Q(ral[5]), .D(ra[5]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_4_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[3]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[4]), .Q(ral[4]), .D(ra[4]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[2]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[3]), .Q(ral[3]), .D(ra[3]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[1]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[2]), .Q(ral[2]), .D(ra[2]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(ralb[0]), .SC_EN(scan_en), .CD(resetb), .QN(ralb[1]), .Q(ral[1]), .D(ra[1]), .CP(aclkw)); |
| s8fmlt_dffsc raddlat_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .SC_INB(scan_inb), .SC_EN(scan_en), .CD(resetb), .QN(ralb[0]), .Q(ral[0]), .D(ra[0]), .CP(aclkw)); |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_dinpg_atpg (vpwr, vpb, vnb, vgnd, scan_outb, clk, di, pa, pw, reset, scan_en, scan_inb, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb; |
| |
| input clk, pw, reset, scan_en, scan_inb, scan_mode; |
| |
| input [7:0] di; |
| input [6:0] pa; |
| |
| // Buses in the design |
| |
| wire [6:0] paib; |
| |
| wire [6:0] pai; |
| |
| wire [7:0] dii; |
| |
| wire [7:0] diib; |
| |
| not I456 ( rstb, reset); |
| s8fmlt_dffsc pwlat (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(pwib), .D(pw), .Q(pwi), .CD(rstb), .SC_EN(scan_en), .SC_INB(scan_inb)); |
| s8fmlt_dffsc dilat_7_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[7]), .D(di[7]), .Q(dii[7]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[6])); |
| s8fmlt_dffsc dilat_6_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[6]), .D(di[6]), .Q(dii[6]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[5])); |
| s8fmlt_dffsc dilat_5_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[5]), .D(di[5]), .Q(dii[5]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[4])); |
| s8fmlt_dffsc dilat_4_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[4]), .D(di[4]), .Q(dii[4]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[3])); |
| s8fmlt_dffsc dilat_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[3]), .D(di[3]), .Q(dii[3]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[2])); |
| s8fmlt_dffsc dilat_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[2]), .D(di[2]), .Q(dii[2]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[1])); |
| s8fmlt_dffsc dilat_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[1]), .D(di[1]), .Q(dii[1]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[0])); |
| s8fmlt_dffsc dilat_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(diib[0]), .D(di[0]), .Q(dii[0]), .CD(rstb), .SC_EN(scan_en), .SC_INB(pwib)); |
| s8fmlt_dffsc palat_6_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[6]), .D(pa[6]), .Q(pai[6]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[5])); |
| s8fmlt_dffsc palat_5_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[5]), .D(pa[5]), .Q(pai[5]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[4])); |
| s8fmlt_dffsc palat_4_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[4]), .D(pa[4]), .Q(pai[4]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[3])); |
| s8fmlt_dffsc palat_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[3]), .D(pa[3]), .Q(pai[3]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[2])); |
| s8fmlt_dffsc palat_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[2]), .D(pa[2]), .Q(pai[2]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[1])); |
| s8fmlt_dffsc palat_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[1]), .D(pa[1]), .Q(pai[1]), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[0])); |
| s8fmlt_dffsc palat_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(paib[0]), .D(pa[0]), .Q(pai[0]), .CD(rstb), .SC_EN(scan_en), .SC_INB(diib[7])); |
| s8fmlt_dffsc pwplat (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CP(clk), .QN(scan_outb), .D(pwib), .Q(pwpi), .CD(rstb), .SC_EN(scan_en), .SC_INB(paib[6])); |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_spine16x64_atpg (vpwr, vpb, vnb, vgnd, dout, scan_out, clk, iso, resetb, scan_in, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| input clk, iso, resetb, scan_in, scan_mode; |
| |
| output [63:0] dout; |
| |
| s8fmlt_sa64 sa64 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scan_in), .scan_out(scan_out), .iso(iso), .out(dout[63:0])); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_sa64 (vpwr, vpb, vnb, vgnd, scan_out, out, clk, iso, resetb, scan_in, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| |
| input clk, iso, resetb, scan_in, scan_mode; |
| |
| |
| inout [63:0] out; |
| |
| // Buses in the design |
| |
| wire [2:0] scano; |
| |
| |
| s8fmlt_sa16_fm sa8_fm_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .out({out[63], out[62], out[61], out[60], out[59], out[58], out[57], out[56], out[55], out[54], out[53], out[52], out[51], out[50], out[49], out[48]}), |
| .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[2]), .scan_out(scan_out), .iso(iso)); |
| s8fmlt_sa16_fm sa8_fm_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .out({out[47], out[46], out[45], out[44], out[43], out[42], out[41], out[40], out[39], out[38], out[37], out[36], out[35], out[34], out[33], out[32]}), |
| .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[1]), .scan_out(scano[2]), .iso(iso)); |
| s8fmlt_sa16_fm sa8_fm_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .out({out[31], out[30], out[29], out[28], out[27], out[26], out[25], out[24], out[23], out[22], out[21], out[20], out[19], out[18], out[17], out[16]}), |
| .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[0]), .scan_out(scano[1]), .iso(iso)); |
| s8fmlt_sa16_fm sa8_fm_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .out({out[15], out[14], out[13], out[12], out[11], out[10], out[9], out[8], out[7], out[6], out[5], out[4], out[3], out[2], out[1], out[0]}), .resetb(resetb), .clk(clk), |
| .scan_mode(scan_mode), .scan_in(scan_in), .scan_out(scano[0]), .iso(iso)); |
| |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_sa16_fm (vpwr, vpb, vnb, vgnd, scan_out, out, clk, iso, resetb, scan_in, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| input clk, iso, resetb, scan_in, scan_mode; |
| |
| |
| inout [15:0] out; |
| |
| // Buses in the design |
| |
| wire [14:0] scano; |
| |
| |
| |
| s8fmlt_saout saout_fm_15_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[14]), .scan_out(scan_out), .iso(iso), .out(out[15])); |
| s8fmlt_saout saout_fm_14_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[13]), .scan_out(scano[14]), .iso(iso), .out(out[14])); |
| s8fmlt_saout saout_fm_13_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[12]), .scan_out(scano[13]), .iso(iso), .out(out[13])); |
| s8fmlt_saout saout_fm_12_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[11]), .scan_out(scano[12]), .iso(iso), .out(out[12])); |
| s8fmlt_saout saout_fm_11_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[10]), .scan_out(scano[11]), .iso(iso), .out(out[11])); |
| s8fmlt_saout saout_fm_10_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[9]), .scan_out(scano[10]), .iso(iso), .out(out[10])); |
| s8fmlt_saout saout_fm_9_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[8]), .scan_out(scano[9]), .iso(iso), .out(out[9])); |
| s8fmlt_saout saout_fm_8_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[7]), .scan_out(scano[8]), .iso(iso), .out(out[8])); |
| s8fmlt_saout saout_fm_7_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[6]), .scan_out(scano[7]), .iso(iso), .out(out[7])); |
| s8fmlt_saout saout_fm_6_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[5]), .scan_out(scano[6]), .iso(iso), .out(out[6])); |
| s8fmlt_saout saout_fm_5_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[4]), .scan_out(scano[5]), .iso(iso), .out(out[5])); |
| s8fmlt_saout saout_fm_4_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[3]), .scan_out(scano[4]), .iso(iso), .out(out[4])); |
| s8fmlt_saout saout_fm_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[2]), .scan_out(scano[3]), .iso(iso), .out(out[3])); |
| s8fmlt_saout saout_fm_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[1]), .scan_out(scano[2]), .iso(iso), .out(out[2])); |
| s8fmlt_saout saout_fm_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scano[0]), .scan_out(scano[1]), .iso(iso), .out(out[1])); |
| s8fmlt_saout saout_fm_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_mode(scan_mode), .scan_in(scan_in), .scan_out(scano[0]), .iso(iso), .out(out[0])); |
| |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_saout (vpwr, vpb, vnb, vgnd, scan_out, out, clk, iso, resetb, scan_in, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| inout out; |
| |
| input clk, iso, resetb, scan_in, scan_mode; |
| |
| not I1 (isob,iso); |
| and I2 (out,isob,saout); |
| s8fmlt_dout_scan dout_scan (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .resetb(resetb), .clk(clk), .scan_in(scan_in), .scan_mode(scan_mode), .data(saout), .scan_out(scan_out)); |
| //s8fmlt_dlat dlat ( .saen3x(saen3), .reset(reset), .keeper(saout), .vpwr(vpwr), .vgnd(vgnd), .vnb(vnb), .vpb(vpb)); |
| //s8fmlt_dobuf dobuf ( .iso(iso), .vpwr(vpwr), .vgnd(vgnd), .vpb(vpb), .in(saout), .out(out), .vnb(vnb)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_dout_scan (vpwr, vpb, vnb, vgnd, scan_out, data, clk, resetb, scan_in, scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out; |
| |
| inout data; |
| |
| input clk, resetb, scan_in, scan_mode; |
| |
| |
| not I1 (data,scan_outb); |
| s8fmlt_scs8ls_dfrbp_1 scan_ff (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(scan_outb), .CLK(clk), .D(scan_in), .Q(scan_out), .RESETB(resetb)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_mpcont_atpg (vpwr, vpb, vnb, vgnd, scan_out, scanb_mp_tm, axa, clk, iso, mode, reset, scan_en, scan_in, scan_mode, scan_sa_mp, seq); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_out, scanb_mp_tm; |
| |
| input axa, clk, iso, reset, scan_en, scan_in, scan_mode, scan_sa_mp; |
| |
| |
| input [3:0] mode; |
| input [1:0] seq; |
| |
| // Buses in the design |
| |
| wire [3:0] modee; |
| |
| wire [1:0] seqe; |
| |
| wire [3:0] bulkb_n; |
| |
| |
| not scan_out_inv ( scanb_sa_mp, scan_sa_mp); |
| nor scan_out_nor ( scan_out, iso, scanb_sa_mp); |
| |
| s8fmlt_mode_logic_lite I132 (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd),.axa(axa), .seqe(seqe[1:0]), .seq(seq[1:0]), .mode(mode[3:0]), .modee(modee[3:0])); |
| |
| s8fmlt_mpcon_top mpcon_top (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .aclk(clk), .scan_outb(scanb_mp_tm), .scan_en(scan_en), |
| .scan_mode(scan_mode), .scan_in(scan_in), .mode(modee[3:0]), .seq(seqe[1:0]), .reset(reset)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_mpcon_top (vpwr, vpb, vnb, vgnd, |
| mode, seq, reset, aclk, |
| scan_in, scan_en, scan_outb, |
| scan_mode); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb ; |
| input aclk, reset, scan_en, scan_in; |
| input [3:0] mode; |
| input [1:0] seq; |
| input scan_mode; |
| |
| |
| s8fmlt_mpcon mpcon (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_outb ( scan_outb ), .aclk ( aclk ), |
| .scan_en ( scan_en), .scan_in ( scan_in), .mode ( mode ), .seq ( seq ), |
| .reset ( reset)); |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_mpcon (vpwr, vpb, vnb, vgnd, |
| mode, seq, reset, aclk, |
| scan_in, scan_en, scan_outb |
| ); |
| input vpwr, vpb, vnb, vgnd; |
| input aclk, reset; |
| input scan_en, scan_in; |
| output scan_outb ; |
| input [3:0] mode; |
| input [1:0] seq; |
| wire [0:3] fi_mode; |
| wire [0:1] fi_seq; |
| |
| // This seems like superfluous logic |
| //scs8lp_and2b_2 U179 ( .B ( scan_mode), .AN ( scano2i), .X ( scan_outb)); |
| // clean up spagheti route |
| //scs8lp_and2b_2 U179 ( .B ( scan_mode), .AN ( scan_out), .X ( scan_outb)); |
| // must use primitive to support both pg and non-pg sims |
| wire scan_mode=1'b1; |
| and (scan_outb, scan_mode, not_scan_out); |
| not (not_scan_out, scan_out); |
| |
| not U198 (n58, reset); |
| s8fmlt_sdfrtp_2 fi_seq_reg_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( fi_seq_0_ ), .D ( seq[1]), .Q ( scan_out), .RESETB ( n58)); |
| s8fmlt_sdfrtp_2 fi_seq_reg_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( fi_mode[3] ), .D ( seq[0]), .Q ( fi_seq_0_), .RESETB ( n58)); |
| s8fmlt_sdfrtp_2 fi_mode_reg_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( fi_mode[2] ), .D ( mode[3]), .Q ( fi_mode[3]), .RESETB ( n58)); |
| s8fmlt_sdfrtp_2 fi_mode_reg_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( fi_mode[1] ), .D ( mode[2]), .Q ( fi_mode[2]), .RESETB ( n58)); |
| s8fmlt_sdfrtp_2 fi_mode_reg_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( fi_mode[0] ), .D ( mode[1]), .Q ( fi_mode[1]), .RESETB ( n58)); |
| s8fmlt_sdfrtp_2 fi_mode_reg_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .CLK (aclk), .SCE ( scan_en ), .SCD ( scan_in ), .D ( mode[0]), .Q ( fi_mode[0]), .RESETB ( n58)); |
| // Start scan chain here |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_mode_logic_lite (vpwr, vpb, vnb, vgnd, modee, seqe, axa, mode, seq); |
| input vpwr, vpb, vnb, vgnd; |
| |
| input axa; |
| |
| output [3:0] modee; |
| output [1:0] seqe; |
| |
| input [1:0] seq; |
| input [3:0] mode; |
| |
| // Buses in the design |
| |
| wire [0:1] seqb; |
| |
| |
| |
| nand ( strong0,strong1 ) I1488 ( net28, m3, m1, m0b); |
| nand ( strong0,strong1 ) I1490 ( net36, m3, m2, ax); |
| nand ( strong0,strong1 ) I1489 ( modee[1], m1b_2, net36, net52); |
| nand ( strong0,strong1 ) I1491 ( net52, m3, m0, ax); |
| nand ( strong0,strong1 ) I1492 ( net60, m3, m2, ax); |
| not ( strong0,strong1 ) I1483 ( m3b, mode[3]); |
| not ( strong0,strong1 ) inv2s0 ( seqe[0], seqb[0]); |
| not ( strong0,strong1 ) I1496 ( axb, axa); |
| not ( strong0,strong1 ) inv1m0 ( m0b, mode[0]); |
| not ( strong0,strong1 ) I1502 ( net150, seq[0]); |
| not ( strong0,strong1 ) inv1m1 ( m1b, mode[1]); |
| not ( strong0,strong1 ) I1484 ( m2, m2b); |
| not ( strong0,strong1 ) I1486 ( m1, m1b); |
| not ( strong0,strong1 ) inv1s1 ( seqb[1], net72); |
| not ( strong0,strong1 ) I1497 ( ax, axb); |
| not ( strong0,strong1 ) I1503 ( net180, seq[1]); |
| not ( strong0,strong1 ) I1487 ( m0, m0b); |
| not ( strong0,strong1 ) I1482 ( m2b, mode[2]); |
| not ( strong0,strong1 ) I1485 ( m3, m3b); |
| not ( strong0,strong1 ) I1504 ( net204, net180); |
| not ( strong0,strong1 ) inv2s1 ( seqe[1], seqb[1]); |
| not ( strong0,strong1 ) inv1s0 ( seqb[0], net66); |
| not ( strong0,strong1 ) I1505 ( net210, net150); |
| not ( strong0,strong1 ) I1506 ( m0b_2, m0); |
| not ( strong0,strong1 ) I1507 ( m1b_2, m1); |
| not ( strong0,strong1 ) I1508 ( m2b_2, m2); |
| not ( strong0,strong1 ) I1512 ( net66, net84); |
| not ( strong0,strong1 ) I1511 ( net72, net78); |
| not ( strong0,strong1 ) I1510 ( net78, net204); |
| not ( strong0,strong1 ) I1509 ( net84, net210); |
| nand I1478 ( net216, m3, m1b_2); |
| nand I1479 ( net223, m3, m0); |
| nand I1480 ( modee[3], net216, net223); |
| nand I1481 ( modee[2], m2b_2, net28); |
| nand I1493 ( modee[0], m0b_2, net60); |
| |
| endmodule |
| |
| |
| `timescale 1ns/1ps |
| module s8fmlt_analog_top_atpg (vpwr, vpb, vnb, vgnd, scanb_tm_dpg, clk, pnb, reset, scan_en, scan_mode, scanb_mp_tm, tm); |
| input vpwr, vpb, vnb, vgnd; |
| output scanb_tm_dpg; |
| |
| input clk, pnb, reset, scan_en, scan_mode, scanb_mp_tm; |
| |
| input [4:0] tm; |
| |
| wire [3:0] ndacdel; |
| |
| wire [3:0] pdacdel; |
| |
| wire [5:0] isao; |
| |
| wire [2:0] itimo; |
| |
| |
| s8fmlt_tmcont_top tmcont (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_outb(scanb_tm_dpg), .scan_inb(scanb_mp_tm), .reset(reset), |
| .clk(clk), .scan_en(scan_en), .scan_mode(scan_mode), |
| .tm(tm[4:0]), |
| .pnb(pnb)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_tmcont_top (vpwr, vpb, vnb, vgnd, scan_outb, clk, pnb, reset, scan_en, scan_inb, scan_mode, tm); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb; |
| |
| input clk, pnb, reset, scan_en, scan_inb, scan_mode; |
| |
| input [4:0] tm; |
| |
| |
| s8fmlt_tmcont_nsw tmcont_nsw (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_outb(scan_outb), .scan_inb(scan_inb), .scan_en(scan_en), |
| .pnb(pnb), |
| .tm(tm[4:0]), .reset(reset), |
| .clk(clk), .scan_mode(scan_mode)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_tmcont_nsw (vpwr, vpb, vnb, vgnd, clk, pnb, reset, scan_en, scan_inb, scan_mode, tm, scan_outb); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb; |
| |
| input clk, pnb, reset, scan_en, scan_inb, scan_mode; |
| |
| input [4:0] tm; |
| |
| // Buses in the design |
| |
| wire [4:0] tm_buf; |
| |
| |
| |
| s8fmlt_tmcont_logic_pnr tmcont_logic (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_inb(scan_inb), .scan_outb(scan_outb), |
| .scan_mode(scan_mode), |
| .clk(clk), .pnb(pnb), .tm(tm[4:0]), .scan_en(scan_en), .reset(reset)); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_tmcont_logic_pnr (vpwr, vpb, vnb, vgnd, clk, pnb, reset, scan_en, scan_inb, |
| scan_mode, tm,scan_outb); |
| input vpwr, vpb, vnb, vgnd; |
| |
| output scan_outb; |
| |
| input clk, pnb, reset, scan_en, scan_inb, scan_mode; |
| |
| input [4:0] tm; |
| |
| // Buses in the design |
| |
| wire [3:0] tm_ab1; |
| |
| wire [3:0] tm_res; |
| |
| wire [3:0] tm_ab2; |
| |
| wire [3:0] tm_ltm; |
| |
| wire [3:0] tm_sr; |
| |
| wire [3:0] tm_mm; |
| |
| wire [3:0] tm_hv; |
| |
| wire [3:0] tm_nr; |
| |
| wire [4:0] tmlb; |
| |
| wire [4:0] tml; |
| |
| |
| |
| s8fmlt_tmcont_in_pnr tmcont_in (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .scan_inb(scan_inb), .scan_outb(scan_outb), .clk(clk), .tm(tm[4:0]), .scan_en(scan_en), .reset(reset), .pnb(pnb)); |
| |
| endmodule |
| |
| `timescale 1ns/1ps |
| module s8fmlt_tmcont_in_pnr (vpwr, vpb, vnb, vgnd, scan_outb, clk, pnb, reset, scan_en, scan_inb, tm); |
| input vpwr, vpb, vnb, vgnd; |
| output scan_outb; |
| |
| input clk, pnb, reset, scan_en, scan_inb; |
| |
| |
| input [4:0] tm; |
| |
| wire [4:0] tml,tmlb; |
| |
| s8fmlt_scs8ls_sdfrbp_1 tmlat_4_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(tmlb[4]), .CLK(clk), .SCE(scan_en), .SCD(tml[3]), .RESETB(resetb), .D(tm[4]), .Q(tml[4])); |
| s8fmlt_scs8ls_sdfrbp_1 tmlat_3_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(tmlb[3]), .CLK(clk), .SCE(scan_en), .SCD(tml[2]), .RESETB(resetb), .D(tm[3]), .Q(tml[3])); |
| s8fmlt_scs8ls_sdfrbp_1 tmlat_2_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(tmlb[2]), .CLK(clk), .SCE(scan_en), .SCD(tml[1]), .RESETB(resetb), .D(tm[2]), .Q(tml[2])); |
| s8fmlt_scs8ls_sdfrbp_1 tmlat_1_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(tmlb[1]), .CLK(clk), .SCE(scan_en), .SCD(tml[0]), .RESETB(resetb), .D(tm[1]), .Q(tml[1])); |
| s8fmlt_scs8ls_sdfrbp_1 tmlat_0_ (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(tmlb[0]), .CLK(clk), .SCE(scan_en), .SCD(pnbl), .RESETB(resetb), .D(tm[0]), .Q(tml[0])); |
| s8fmlt_scs8ls_sdfrbp_1 pnblat (.vpwr(vpwr), .vpb(vpb), .vnb(vnb), .vgnd(vgnd), .QN(pnblb), .CLK(clk), .SCE(scan_en), .SCD(scan_in), .RESETB(resetb), .D(pnb), .Q(pnbl)); |
| //scs8ls_inv_2 tmlb4_inv ( .A(tmlb[4]), .Y(net41)); |
| //scs8ls_inv_1 scanb_inv ( .A(scan_inb), .Y(scan_in)); |
| //scs8ls_inv_1 scan_out_inv ( .A(net41), .Y(scan_outb)); |
| //scs8ls_inv_1 reset_inv ( .A(reset), .Y(resetb)); |
| not tmlb4_inv ( net41, tmlb[4] ); |
| not scanb_inv ( scan_in, scan_inb ); |
| not scan_out_inv ( scan_outb, net41 ); |
| not reset_inv ( resetb, reset ); |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_dffsc (vpwr, vpb, vnb, vgnd, Q, QN, CD, CP, D, SC_EN, SC_INB); |
| input vpwr, vpb, vnb, vgnd; |
| |
| output Q, QN; |
| input CD, CP, D, SC_EN, SC_INB; |
| wire pwr; |
| |
| not (QN,Q); |
| not (reset,CD); |
| assign pwr=(vpwr===1'b1)&(vpb===1'b1)&(vnb===1'b0)&(vgnd===1'b0); |
| wire din =SC_EN ? !SC_INB : D; |
| reg nfr; |
| |
| s8fmlt_dffsc_udp #1 Idffsc_udp (Q,din,CP,reset,nfr,pwr); |
| |
| endmodule |
| |
| primitive s8fmlt_dffsc_udp (q,d,cp,r,nfr,pwr); |
| output q; |
| input d,cp,r,nfr,pwr; |
| reg q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // d cp r nfr pwr: Qt : Qt+1 |
| |
| 1 (01) 0 ? 1 : ? : 1; // clocked data |
| 0 (01) 0 ? 1 : ? : 0; |
| |
| 0 (01) x ? 1 : ? : 0; // pessimism |
| 0 ? x ? 1 : 0 : 0; // pessimism |
| |
| 1 0 x ? 1 : 0 : 0; // pessimism |
| 1 x (?x) ? 1 : 0 : 0; // pessimism |
| 1 1 (?x) ? 1 : 0 : 0; // pessimism |
| |
| x 0 x ? 1 : 0 : 0; // pessimism |
| x x (?x) ? 1 : 0 : 0; // pessimism |
| x 1 (?x) ? 1 : 0 : 0; // pessimism |
| |
| 1 (x1) 0 ? 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 ? 1 : 0 : 0; |
| 1 (0x) 0 ? 1 : 1 : 1; |
| 0 (0x) 0 ? 1 : 0 : 0; |
| |
| |
| ? ? 1 ? 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? ? 1 : ? : -; // ignore falling clock |
| * ? ? ? 1 : ? : -; // ignore the edges on data |
| |
| ? ? (?0) ? 1 : ? : -; // ignore the edges on clear |
| ? ? ? * ? : ? : x; // corrupt output when the nitifier toggles |
| ? ? ? ? 0 : ? : x; // corrupt output when the nitifier toggles |
| |
| endtable |
| |
| endprimitive |
| `timescale 1ns/1ps |
| module s8fmlt_sdfrtp_2 (vpwr, vpb, vnb, vgnd, RESETB,CLK,D,Q,SCD,SCE); |
| input vpwr, vpb, vnb, vgnd; |
| |
| output Q; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| wire pwr; |
| reg nfr; |
| |
| not (QN,Q); |
| not (reset,RESETB); |
| assign pwr=(vpwr===1'b1)&(vpb===1'b1)&(vnb===1'b0)&(vgnd===1'b0); |
| assign mux_out = (SCE) ? SCD : D; |
| s8fmlt_sdfrtp_udp #1 (buf_Q , mux_out , CLK , reset, nfr, pwr) ; |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| |
| primitive s8fmlt_sdfrtp_udp (Q, D, CP, R, NFR, PWR); |
| output Q; |
| input D, CP, R, NFR, PWR; |
| reg Q; |
| |
| // FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH |
| // ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). |
| |
| table |
| |
| // D CP R NFR PWR : Qt : Qt+1 |
| |
| 1 (01) 0 ? 1 : ? : 1; // clocked data |
| 0 (01) 0 ? 1 : ? : 0; |
| |
| 0 (01) x ? 1 : ? : 0; // pessimism |
| 0 ? x ? 1 : 0 : 0; // pessimism |
| |
| 1 0 x ? 1 : 0 : 0; // pessimism |
| 1 x (?x) ? 1 : 0 : 0; // pessimism |
| 1 1 (?x) ? 1 : 0 : 0; // pessimism |
| |
| x 0 x ? 1 : 0 : 0; // pessimism |
| x x (?x) ? 1 : 0 : 0; // pessimism |
| x 1 (?x) ? 1 : 0 : 0; // pessimism |
| |
| 1 (x1) 0 ? 1 : 1 : 1; // reducing pessimism |
| 0 (x1) 0 ? 1 : 0 : 0; |
| 1 (0x) 0 ? 1 : 1 : 1; |
| 0 (0x) 0 ? 1 : 0 : 0; |
| |
| |
| ? ? 1 ? 1 : ? : 0; // asynchronous clear |
| |
| ? (?0) ? ? 1 : ? : -; // ignore falling clock |
| ? (1x) ? ? 1 : ? : -; // ignore falling clock |
| * ? ? ? 1 : ? : -; // ignore the edges on data |
| |
| ? ? (?0) ? 1 : ? : -; // ignore the edges on clear |
| ? ? ? * ? : ? : x; // corrupt output when the nitifier toggles |
| |
| ? ? ? ? 0 : ? : x; // corrupt output when power bad |
| |
| endtable |
| endprimitive |
| `timescale 1ns/1ps |
| module s8fmlt_scs8ls_sdfrbp_1 (vpwr, vpb, vnb, vgnd, RESETB,CLK,D,Q,SCD,SCE,QN); |
| input vpwr, vpb, vnb, vgnd; |
| |
| output Q,QN; |
| input CLK,D,SCD,SCE,RESETB; |
| wire buf_Q, reset, mux_out; |
| wire pwr; |
| reg nfr; |
| |
| not (QN,Q); |
| not (reset,RESETB); |
| assign pwr=(vpwr===1'b1)&(vpb===1'b1)&(vnb===1'b0)&(vgnd===1'b0); |
| assign mux_out = (SCE) ? SCD : D; |
| s8fmlt_sdfrtp_udp #1 ( buf_Q , mux_out , CLK , reset, nfr,pwr) ; |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
| `timescale 1ns/1ps |
| module s8fmlt_scs8ls_dfrbp_1 (vpwr, vpb, vnb, vgnd, RESETB,CLK,D,Q,QN); |
| input vpwr, vpb, vnb, vgnd; |
| |
| output Q,QN; |
| input CLK,D,RESETB; |
| wire buf_Q, reset; |
| wire pwr; |
| reg nfr; |
| |
| assign pwr=(vpwr===1'b1)&(vpb===1'b1)&(vnb===1'b0)&(vgnd===1'b0); |
| |
| not (QN,Q); |
| not (reset,RESETB); |
| |
| s8fmlt_sdfrtp_udp #1 (buf_Q , D , CLK , reset, nfr,pwr) ; |
| |
| buf (Q,buf_Q); |
| |
| endmodule |
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