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foss-eda-tools / skywater-src-nda / 65e952e33a1939082b02075226e3a16de2965d4c / . / s8fmlt / V0.1.0 / verilog / s8fmlt_32k_sys.v
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// ================================================
// Copyright 2013, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by United States copyright laws and international
// treaty provisions. Therefore, you must treat this software like any
// other copyrighted material (e.g., book, or musical recording), with
// the exception that one copy may be made for personal use or
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// representation of this software in any other form (e.g., paper,
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// purpose. Cypress reserves the right to make changes without further
// notice to the materials described herein. Cypress does not assume any
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// circuit described herein. Cypress' products described herein are
// not authorized for use as components in life-support devices.
//
// This software is protected by and subject to worldwide patent
// coverage, including U.S. and foreign patents. Use may be limited by
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// ===============================================
// File : $File: //depot/icm/proj/s8fmlt/icmrel/ipVault/opus/s8fmlt/s8fmlt_32k_sys/behavioral/verilog.v $
// Author : Iustin Ignatescu (IXI)
// Date : 09/2012
// $Revision: 1 $
// ===============================================
// Description: this the system level behavioral model for the s8fmlt_32k_sys
// flash macro. This is a stand alone model which models the entire system including
// pump, iref, vdac logic previously modeled in separate blocks
//----------------------------------------------------------------------
`timescale 1ns/1ps
module s8fmlt_32k_sys ( amuxbusa, amuxbusb, dout, scan_out1, scan_out2,
`ifdef USE_PG_PIN
vpwri_fm,
`endif
xy_out, axa, bdac, ca, cdac, clk, di, idac, iref, iso, mdac, mode, ndac,
pa, pclk, pd1, pd2, pdac, pe, pnb, pw, ra, reset, scan_en, scan_in1, scan_in2,
scan_mode, sdac, seq, sleep, tm, turbo_b, itimo_nvl, VPOS, VNEG, VMARG_AUX,
`ifdef USE_PG_PIN
vccd, vgnd, vnb, vpb, vpb_sw,
`endif
vref );
parameter CODEFILE = "s8fmlt_32k.rom" ;
//----------------------------------------------------------------------------------------------------
// configuratioon parameters
localparam AADDR_BITS = 1; // special sector select bit - axa
localparam BADDR_BITS = 0; // no ba address bits
localparam RADDR_BITS = 8; // 512 rows in one sector one plane
localparam CADDR_BITS = 4; // 16 columns
localparam DADDR_BITS = 0; // Da bus not used in 64k lite
localparam PADDR_BITS = 7; // 128x8bit latches
localparam SRADDR_BITS = 3; // number of bits required to address a special row in a special sector - 8 special rows
localparam SBADDR_BITS = 0; //number of ba bits required to address one special sector
localparam ADDR_BITS = AADDR_BITS+BADDR_BITS+RADDR_BITS+CADDR_BITS; //ba is 0 for 64k lite
localparam PLADDR_BITS = 0; // Bits required to decode the plane. One plane in 64k lite
localparam TADDR_BITS = 5; // new implementation of test mode select
localparam SEQ_SIZE = 2; // sequence bus size
localparam MODE_SIZE = 4; // mode bus size
localparam DI_SIZE = 8; // input size
localparam DO_SIZE = 64; // output size
localparam READ = 4'b0000; // read mode
localparam PREPRG = 4'b0001; // preprogram mode
localparam PWRALL = 4'b0010; // page write all
localparam PS_IDLE = 4'b0011; // Pseudo idle mode
localparam CLR_PAGE = 4'b0100; // clear page latches mode
localparam RSTHV = 4'b0101; // reset hv mode
localparam ERS_BK = 4'b1001; // erase bulk
localparam ERS_SC = 4'b1010; // erase sector mode; not used in 64k lite
localparam ERS_WL = 4'b1011; // erase sub-sector mode
localparam PRG_BK_ALL = 4'b1100; // program bulk all rows
localparam PRG_BK = 4'b1101; // program bulk (odd or even rows)
localparam PRG_SC = 4'b1110; // program sector (odd or even rows); not used in 64k lite
localparam PRG_WL = 4'b1111; // program word line
localparam MEM_SIZE = 2**ADDR_BITS ; // memory size is 2 to the address size
localparam COLUMNS = 2**CADDR_BITS ; // number of "do's" on a row;
localparam PAGE_SIZE = 2**PADDR_BITS ; // number of page latces; also number of di's on a row
localparam SPEC_SECTOR_ROWS = 2**SRADDR_BITS;
localparam SECTOR_ROWS = 2**RADDR_BITS;
localparam SECTORS = 2**BADDR_BITS;
localparam SPEC_SECTORS = 2**SBADDR_BITS;
localparam PLANES = 2**PLADDR_BITS;
`ifdef functional
parameter S8FMLT_32K_TAA = 48; //AC 3.1
`endif
localparam DOH = 1; //Data out hold time AC 3.7
localparam S8FMLT_32K_TPWR = 1000; //AC 3.24
localparam S8FMLT_32K_TRST = 0;
localparam S8FMLT_32K_TAW = 6; //AC 3.5 width of clk pulse. Used to delay clk for all notifiers to settle
localparam ACLK_DELAY = S8FMLT_32K_TAW + 0.1;
localparam S8FMLT_32K_TCY = 51; //AC 3.2
localparam S8FMLT_32K_TS1 = 1000; // AC 3.9
localparam S8FMLT_32K_TS3 = 1000; // AC 3.16
//pump frequency parameter
localparam TPCLK_MIN = 19; //min cycle time for pclk OP.6
localparam TPCLK_MAX = 23; //max cycle time for pclk OP.6
`ifdef S8FMLT_32K_SYS_DISABLE_IREF_STARTUP_DELAY
parameter PWRISA = 0;
parameter PWRITIM= 0;
parameter TTURBO = 100; // turbo be should always be used,even when the start up delay is disabled
`else
parameter PWRISA = 5000; // 5us from power good or sleep to isao good
parameter PWRITIM= 5000; // 5us from power good or sleep to itim good
parameter TTURBO = 5000; // AC 1.25 5us required time for turbo_b to be 0 after iref trim settings
`endif
`ifdef S8FMLT_32K_SYS_DISABLE_MDAC_STARTUP_DELAY
parameter TTMD = 0; // power and active to output valid
parameter TTMD1= 0; // settle time for mdac change
parameter TTMD2= 0; // vdac off (inactive)
`else
parameter TTMD = 50000; // AC 3.17 power and active to output valid
parameter TTMD1= 25000; // AC 3.18 settle time for mdac change
parameter TTMD2= 15000; // AC 3.19 vdac off (inactive)
`endif
`ifdef USE_PG_PIN
`else
supply1 vpb_sw;
supply1 vpb;
supply1 vccd;
supply0 vnb;
supply0 vgnd;
`endif
input sleep;
input [3:0] bdac;
`ifdef USE_PG_PIN
input vpb_sw;
input vpb;
`endif
input scan_in1;
`ifdef USE_PG_PIN
input vccd;
`endif
input [3:0] mode;
output [63:0] dout;
input pe;
input [7:0] di;
input iso;
input reset;
`ifdef USE_PG_PIN
input vnb;
`endif
input [1:0] seq;
input scan_en;
input iref;
input pw;
input turbo_b;
inout amuxbusb;
input axa;
`ifdef USE_PG_PIN
input vgnd;
`endif
inout amuxbusa;
output scan_out1;
input [2:0] sdac;
input scan_in2;
input pnb;
input clk;
input pd1;
input pd2;
input vref;
output scan_out2;
input pclk;
input [3:0] ca;
input [2:0] cdac;
input [3:0] pdac;
input scan_mode;
input [6:0] pa;
`ifdef USE_PG_PIN
output vpwri_fm;
`endif
output xy_out;
input [4:0] tm;
input [7:0] ra;
input [4:0] idac;
input [7:0] mdac;
input [3:0] ndac;
output VPOS, VNEG, VMARG_AUX;
output itimo_nvl;
reg [ADDR_BITS-1:0] address;
reg [MODE_SIZE-1:0] mode_l,prev_mode;
reg [SEQ_SIZE-1:0] seq_l,prev_seq;
reg [MEM_SIZE-1:0] status;
reg [MEM_SIZE-1:0] re_program;
reg [DO_SIZE-1:0] memory [MEM_SIZE-1:0];
reg [DI_SIZE-1:0] page_latch [PAGE_SIZE-1:0];
// reg prg,ers;
reg busy; // flag that keeps trak of on going HV operations
// wire [DO_SIZE-1:0] dout;
reg [DO_SIZE-1:0] douti;
reg preprg_flag;
reg pwrall_flag;
reg page_clr_flag;
reg page_corrupt_flag;
reg reset_hv;
reg sequence_good; // flag that tracks propper sequencing in the HV modes
reg mode_good;
reg [DO_SIZE-1:0] fm_do_reg;
reg [PADDR_BITS-1:0] pa_l;
reg [DI_SIZE-1:0] di_l;
reg pw_l;
reg pnb_l;
reg [TADDR_BITS-1:0] tm_l;
reg reset_x;
// --- NOTIFIERS ---
reg notifier_iso,notifier_rst,notifier_rstw, notifier_tbb, notifier_pd2, notifier_clk, notifier_pe, notifier_scan1, notifier_scan2, notifier_pa, notifier_pw, notifier_di,
notifier_addr, notifier_mode, notifier_tm, notifier_seq, notifier_pump,notifier_pnb;
reg addr_timing_error,iso_timing_error,tbb_timing_error,pd2_timing_error,rst_timing_error,clk_timing_error,di_timing_error,pw_timing_error,pa_timing_error,
pe_timing_error,mode_timing_error,seq_timing_error, pump_timing_error,tm_timing_error,pnb_timing_error;
reg reset_notifier_errors;
reg reset_pump_timing_error;
reg ax_d ; //used to delay the inputs to solve any issues with 0 hold time
//reg [BADDR_BITS-1:0] ba_d ;
reg [RADDR_BITS-1:0] ra_d ;
reg [CADDR_BITS-1:0] ca_d ;
reg [MODE_SIZE-1:0] mode_d;
reg [SEQ_SIZE-1:0] seq_d;
reg [DI_SIZE-1:0] di_d;
reg [PADDR_BITS-1:0] pa_d;
reg pw_d;
reg [TADDR_BITS-1:0] tm_d;
reg pnb_d;
reg [ADDR_BITS-1:0] read_address;
reg tm_enpos,tm_enneg; //driven in tm logic
wire dclk ;
wire dpe ;
wire dscan_in1, dscan_in2 ;
wire [6:0] dpa ;
wire dpw ;
wire [7:0] ddi ;
wire [RADDR_BITS-1:0] dra ;
wire [1:0] dseq ;
wire [3:0] dca ;
wire [3:0] dmode ;
wire [3:0] dpdac ;
wire [3:0] dndac ;
wire daxa ;
wire [4:0] dtm;
wire dpnb;
wire dsleep;
wire pd2orsleep;
wire dreset;
wire dturbo_b;
//reg VMARG_AUX_ref;
// comment out; using virtual single plane architecture
//reg [ADDR_BITS-1:0] north_address;
//reg [ADDR_BITS-1:0] south_address;
reg dis_err_msgs;
wire print_enable;
//wire [DO_SIZE-1:0] pa_128bit;
wire gnd_good;
wire power_lv;
wire p_up;
`ifdef ATPG_SIM
wire scan_out1;
wire scan_out2;
wire xy_out = 1'b0;
`else
wire scan_out1 = 1'b0;
wire scan_out2 = 1'b0;
`endif
wire hv_good;
reg pclk_toggle,pclk_pulse;
reg pclk_period_good;
realtime tpclk00,tpclk11,tpclk10;
realtime prev_seq_sample,seq_sample;
wire vref_internal;
wire vlim;
wire iref_isa;
wire iref_itim;
wire read_isa;
wire read_itim;
wire vmargi;
wire vbl;
wire sleep_isa_del;
wire sleep_isa_x;
wire power_isa_del;
wire power_isa_x;
wire sleep_itim_del;
wire sleep_itim_x;
wire power_itim_del;
wire power_itim_x;
wire mdac_on_del;
wire mdac_on_x;
wire mdac_off_del;
wire mdac_off_x;
wire power_good;
wire inhibit_pe;
wire tm_en;
wire VMARG_AUX_int;
reg tm_vmarg, tm_en_nvl;
reg tm_isa,tm_itim;
reg tm_en_vctat;
reg tm_rdhvpl;
reg amuxbusa_int;
reg amuxbusb_int;
reg tm_xydec;
reg tm_disrow;
reg tm_encol;
reg clk_int;
reg clk_delayed;
reg [1:0] power_state;
reg flag_pd2topd1_error; // flag to display error message only once after pd2 or pd1 are sampled
reg flag_pd2topwr_error; // flag to display error message only once after pd2 or pd1 are sampled
reg mdac_x;
reg pnb_mdac_x;
reg tm_en_ttmd2_flag; // keeps track of margin mode return to be after ttmd2 time
reg margin_exit_error;
reg enter_margin_mode;
reg ers_pe_in_seq2;
reg prg_pe_in_seq2;
reg ers_prg_hv_error;
reg sdac_or_idac_x;
realtime pwr_up_time;
realtime pd1_down_time;
realtime pd2_down_time;
realtime reset_down_time;
event read,run_mode;
event pwr_up_trigger;
event pd1_trigger;
event pd2_trigger;
event reset_trigger;
event mdac_trigger;
event pclk_event;
event sdac_or_idac_event;
integer j;
integer pwrisa,pwritim,tturbo; // used for current referecve powerup delay timing
integer ttmd, ttmd1, ttmd2;
//dummy read in marginmode variables
reg [RADDR_BITS+AADDR_BITS-1:0] ra_l;
reg ra_ttmd1;
reg dummy_read_flag;
reg reset_dummy_read_flag;
event trigger_ra_monitor;
event reset_dummy_read_event;
assign pd1_int = 1'b0;
assign pd2_int = 1'b0;
assign pd2orsleep = pd2 || dsleep;
assign vpwri_fm = (vpb_sw!==1'b1)?1'bx:
((pd1_int===1'b0)||(pd2_int===1'b0))?vccd:
((pd1_int===1'b1)&&(pd2_int===1'b1))?1'bz:1'bx;
`ifdef ATPG_SIM
wire scanb_tm_dpg, scanb_mp_tm;
s8fmlt_32k_top_atpg fm32k_top (.vpwr(vpwri_fm), .vpb(vpb), .vnb(vnb), .vgnd(vgnd),
.iso(iso),.reset(reset),.clk(clk),
.scan_en(scan_en),.scan_mode(scan_mode),.scanb_mp_tm(scanb_mp_tm),.scanb_tm_dpg(scanb_tm_dpg),
.scan_in1(dscan_in1),.scan_out1(scan_out1),.scan_in2(dscan_in2),.scan_out2(scan_out2),
.mode(mode),.seq(seq),.ca(ca),.ra({1'b0,ra}),.axa(axa),.di(di),.pa(pa),.pw(pw),
.dout(dout)
);
s8fmlt_analog_top_atpg analog_top(.vpwr(vpwri_fm), .vpb(vpb), .vnb(vnb), .vgnd(vgnd),
.reset(reset),.clk(clk),.scan_mode(scan_mode),
.scan_en(scan_en),.scanb_tm_dpg(scanb_tm_dpg),.scanb_mp_tm(scanb_mp_tm),
.tm(tm),.pnb(pnb)
);
`else // ATPG_SIM
//----------------------------------------------------------------------------------------------------
//power good signals for simple logic
assign p_up = (vccd === 1'b1)&&(vpb===1'b1)&&(vpb_sw===1'b1)&&(vnb===1'b0)&&(vgnd===1'b0)&&(pd1_int===1'b0)&&(pd2_int===1'b0);
assign p_up_analog = (vccd === 1'b1)&&(vpb===1'b1)&&(vpb_sw===1'b1)&&(vnb===1'b0)&&(vgnd===1'b0)&&(pd1_int===1'b0);
assign power_down_analog = (vccd === 1'b1)&&(vpb_sw===1'b1)&&(vgnd===1'b0)&&(pd1_int===1'b1); //used as iso function for VPOS
assign power_down_amux = (vccd === 1'b1)&&(vpb_sw===1'b1)&&(vgnd===1'b0); //used in iso function
assign gnd_good = (vgnd === 1'b0)&&(vnb===1'b0);
//----------------------------------------------------------------------------------------------------
// vref internal logic to check on refsel
assign vref_internal = vref ;
//----------------------------------------------------------------------------------------------------
// vlim logic
assign vlim = (p_up_analog !== 1'b1) ? 1'bx : // if no power drivex
(pd2orsleep === 1'b1) ? 1'b0 : // if sleep and power drive 0
(pd2orsleep !== 1'b0) ? 1'bx : // if sleep is not valid drive x
vref_internal; // will propagate x from vref_internal
//--------------------------------------------------------------------------------------
// isa itim irefm logic
assign iref_isa = (pd2orsleep === 1'b1) ? 1'bz : // needs review after final schematic
(^pd2orsleep === 1'bx) ? 1'bx :
(iref !== 1'b1) ? 1'bx :
(vlim !== 1'b1 ) ? 1'bx :
(sleep_isa_x !== 1'b0) ? 1'bx: // includes sleep recover timing
(power_isa_x !== 1'b0) ? 1'bx: // includes power recover timing
(sdac_or_idac_x !== 1'b0) ? 1'bx: // includes transition time at trim buss change
(^{sdac,idac} === 1'bx) ? 1'bx : 1'b1 ;
always @(sdac or idac)
begin
disable sdac_or_idac_trigger;
#0;
-> sdac_or_idac_event;
end
always @(sdac_or_idac_event)
begin: sdac_or_idac_trigger
sdac_or_idac_x = 1'b1;
#(pwrisa);
sdac_or_idac_x = 1'b0;
end
assign read_isa = tm_isa?amuxbusa:iref_isa; // isa used for read operations will be either iref or external supplied
assign iref_itim = (pd2orsleep === 1'b1) ? 1'bz : // itim z when in sleep (per old s8tesd block)
(^pd2orsleep === 1'bx) ? 1'bx : // sleep needs to be valid
(iref !== 1'b1) ? 1'bx : // iref need to be 1
(sleep_itim_x !== 1'b0) ? 1'bx: // includes sleep recover timing
(power_itim_x !== 1'b0) ? 1'bx: // includes power recover timing
(sdac_or_idac_x !== 1'b0) ? 1'bx: // includes transition time at trim buss change
(^{sdac,idac} === 1'bx) ? 1'bx : 1'b1 ; // trim bits need to be valid
assign read_itim = tm_itim?amuxbusb:iref_itim;// itim used for read operations will be either iref or external supplied
assign itimo_nvl = ((p_up_analog !== 1'b1)||(^tm_itim === 1'bx)) ? 1'bx : ~read_itim ; //tm_itim dirty points to dirty tm buss
//----------------------------------------------------------------------------------------------------
// vctat logic
assign vctat = (p_up_analog !== 1'b1) ? 1'bx :
(^cdac === 1'bx)?1'bx:
(^{dpe===1'b1,tm_en===1'b1,tm_en_vctat,tm_enpos,tm_enneg}===1'bx)?1'bx:
(dpe===1'b1||tm_en===1'b1||tm_en_vctat||tm_enpos||tm_enneg)?vref_internal:1'b0;
//----------------------------------------------------------------------------------------------------
// hv_good logic pumps; pe is not part of the logic being treated separatelly
assign hv_common = ((pclk_toggle === 1'b1) && // checks pclk frequency
(pclk_pulse === 1'b1) && // checks pclk pulse width
(vref_internal === 1'b1) && // vref used for the neg pump
(pump_timing_error === 1'b0) && // ndac/pdac to pe timing error
(vctat === 1'b1) && // vctat used for the pos pump
(^{cdac}!== 1'bx)); // trim bits for the pumps need to be valid
assign hv_neg_good = (hv_common===1'b1) && (^dndac !== 1'bx); // separate check for VNEG
assign hv_pos_good = (hv_common===1'b1) && (^dpdac !== 1'bx); // separate check for VPOS
assign hv_good = hv_neg_good && hv_pos_good; //hv_good is good when both pumps are good
task hv_good_report ();
begin
$display("\t pclk frequency (must be 1) - %b",pclk_toggle);
$display("\t pclk pulse width (must be 1) - %b",pclk_pulse);
$display("\t vref must be 1 - %b",vref);
$display("\t cdac must be valid - %b",cdac );
$display("\t pdac must be valid - %b",dpdac);
$display("\t ndac must be valid - %b",dndac);
$display("\t ndac/pdac timing to pe (must be 1) - %b",pump_timing_error);
end
endtask
//----------------------------------------------------------------------------------------------------
// VPOS / VNEG drive
// Iso only isolates the negative pump; iso pin floating in VPOS
assign (supply1, supply0) VPOS = (power_down_analog===1'b1)?1'b1: // when power_down VPOS is 1
(p_up_analog !== 1'b1) ? 1'bx : //power for the analog block check
(^{pe,tm_enpos} === 1'bx) ? 1'bx : //pump enable check
(pe === 1'b1 || tm_enpos === 1'b1) ? (hv_pos_good?1'b1:1'bx):1'b1; // if the pump is enabled drive 1 if hv good else drive 1(noHV)
assign (supply1, supply0) VNEG = (iso===1'b1)?(gnd_good?1'b0:1'bx): //if iso is 1 check check grounds to be good
(^iso===1'bx)?1'bx: // is iso is bad drive x
(p_up_analog !== 1'b1) ? 1'bx : //power for the analog block check
(^{pe,tm_enneg} === 1'bx) ? 1'bx : //pump enable check
(pe === 1'b1 || tm_enneg === 1'b1) ? (hv_neg_good?1'b0:1'bx):1'b0; // if the pump is enabled drive 0 if hv good else drive 0(noHV)
//----------------------------------------------------------------------------------------------------
// vmargi logic; used in margin reads
assign tm_en = tm_vmarg || tm_en_nvl; //tm_en is now activation the mdac block for margin reads or nvl margin mode
assign vmargi = (p_up_analog !== 1'b1) ? 1'bx: // depends on pd1 only
(^tm_en === 1'bx) ? 1'bx: // tm_en x happens when tm is not clean and will propagate on vmarg or vmarg_aux
(tm_en === 1'b0) ? 1'b0: // active in margin mode test mode
(hv_good !== 1'b1) ? 1'bx: // uses VPOS and VNEG to set the margin mode voltage
(^{mdac,pnb_l}=== 1'bx) ? 1'bx : // pnb and mdac need to be clean
(mdac_on_x === 1'b1) ? 1'bx : // mdac is charged after ttmd
(mdac_x === 1'b1) ? 1'bx : // mdac transition time - ttmd1
(pnb_mdac_x === 1'b1) ? 1'bx : // pnb has to be constant when in margin mode
(tm_en_ttmd2_flag === 1'b1) ? 1'bx : // tm_en needs to stay 0 while the mdac block is discharging
1'b1;
//tm_en_nvl will be x when tm is not clean
assign vmarg = (tm_en_nvl===1'b1) ? 1'bz :
(tm_en_nvl===1'b0) ? vmargi: 1'bx;
assign VMARG_AUX_int = (tm_en_nvl===1'b1) ? ~vmargi :
(tm_en_nvl===1'b0) ? 1'bz : 1'bx;
//monitor changes in ra for marginmode and dummy mode
always @ (ra_l) //sampled ra address
begin
disable ra_monitor;
#0;
-> trigger_ra_monitor;
end
always @(trigger_ra_monitor)
begin: ra_monitor
ra_ttmd1 = 1'b1; //used in dummy read logic and read corrupt during margin mode
#(ttmd1);
ra_ttmd1 = 1'b0;
end
assign ra_margin_mode_dummy = ra_ttmd1 & tm_vmarg;
always @(reset_dummy_read_event)
begin
reset_dummy_read_flag = 1'b1;
#0.1;
reset_dummy_read_flag = 1'b0;
end
always @(posedge reset or posedge ra_margin_mode_dummy or posedge mdac_on_x or posedge mdac_off_x or posedge reset_dummy_read_flag or posedge reset_hv)
begin
if (reset || reset_dummy_read_flag || reset_hv)
begin
dummy_read_flag = 1'b0;
end
else
begin
dummy_read_flag = 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// vbl logic
assign vbl = (p_up_analog !== 1'b1) ? 1'bx: //depends on pd1 only
(tm_rdhvpl === 1'b1) ? 1'bz: //disabled during read plage latch test mode
(^bdac === 1'bx) ? 1'bx:1'b1; // bdac sets the vbl voltage and it need to be valid
//----------------------------------------------------------------------------------------------------
// iref timing
//isa timing depending on sleep and power good
assign #(0,pwrisa) sleep_isa_del = pd2orsleep;
assign sleep_isa_x = (~pd2orsleep) && sleep_isa_del;
assign #(pwrisa,0) power_isa_del = p_up_analog;
assign power_isa_x = power_good && (!power_isa_del);
//itim timing idependig on sleep and power good
assign #(0,pwritim) sleep_itim_del = pd2orsleep;
assign sleep_itim_x = (!pd2orsleep) && sleep_itim_del;
assign #(pwritim,0) power_itim_del = p_up_analog;
assign power_itim_x = power_good && (!power_itim_del);
//----------------------------------------------------------------------------------------------------
// turbo_b timing check to resume read after current settup change
reg wait_for_turbo_b;
realtime turbo_required_detected_time;
realtime negedge_turbo_b_time;
// when trims change or getting out of sleep or getting out of power bad; record the time and set a flag to corrupt eventural read operations
always @(negedge sleep or sdac or idac or posedge p_up)
begin
turbo_required_detected_time = $realtime;
wait_for_turbo_b = 1'b1;
end
//record negedge turbo_b time
always @(negedge turbo_b)
begin
negedge_turbo_b_time = $realtime;
end
//check turbo_b timing to resume correct read opearations
always @(posedge turbo_b)
begin
if (($realtime - turbo_required_detected_time >= tturbo)&&
($realtime - negedge_turbo_b_time >= tturbo))
begin
wait_for_turbo_b = 1'b0;
end
end
//----------------------------------------------------------------------------------------------------
// vdac timing
// ttmd timing - mdac charge
assign #(ttmd,0) mdac_on_del = tm_en;
assign mdac_on_x = tm_en && (~mdac_on_del);
// ttmd1 timing - mdac change
always @(mdac)
begin
disable mdac_tr;
#0;
-> mdac_trigger;
end
always @(mdac_trigger)
begin: mdac_tr
mdac_x = 1'b1;
#(ttmd1);
mdac_x = 1'b0;
end
// ttmd2 timing - mdac discharge
assign #(0,ttmd2) mdac_off_del = tm_en;
assign mdac_off_x = (~tm_en) && mdac_off_del;
wire #0 tm_en_glitch_free = tm_en;
always @(pnb_l or negedge tm_en_glitch_free)
begin
if (tm_en === 1'b0)
begin
pnb_mdac_x = 1'b0;
end
else
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Pnb cannot change state in margin mode in %m @ %d",$time);
pnb_mdac_x = 1'b1;
end
end
always @ (tm_en)
begin
if (tm_en === 1'b0)
begin
tm_en_ttmd2_flag = 1'b0;
end
else
begin
if (mdac_off_x === 1'b1)
begin
tm_en_ttmd2_flag = 1'b1;
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: tm_en is not 0 while mdac is dischargin for ttmd2 time in %m @ %d",$time);
end
end
end
always @(tm_vmarg)
begin
if (tm_vmarg === 1'b1)
begin
enter_margin_mode = 1'b1;
end
else
begin
if ((enter_margin_mode === 1'b1)&&(tm_vmarg === 1'b0))
begin
enter_margin_mode = 1'b0;
margin_exit_error = 1'b1; // set the margin exit error flag when tm_vmarg is 0 after tm_vmarg was 1;
// this flag will reset when reset hv mode is cloked in or if the workarounf s130 is detected
end
end
end
//----------------------------------------------------------------------------------------------------
//
always @(hv_good or dpe or seq_l or dreset or reset_hv or posedge reset_x)
begin
#0; //eliminates race condition between setuphold delayed signals
if ((reset_x === 1'b1)&&(dpe === 1'b1))
begin
ers_prg_hv_error = 1'b1;
end
else if ((dreset === 1'b1)||(reset_hv === 1'b1))
begin
ers_prg_hv_error = 1'b0;
end
else if ((hv_good !== 1'b1)&&(dpe === 1'b1))
begin
ers_prg_hv_error = 1'b1;
end
else if (seq_l === 2'd3)
begin
#1; // wait one ns for the HV operation to finish then reset the error flag
ers_prg_hv_error = 1'b0;
end
end
//----------------------------------------------------------------------------------------------------
// initialize memory based on the CODEFILE
initial
begin
$readmemh(CODEFILE, memory);
for(j = 0;j < MEM_SIZE;j = j + 1)
begin
if (memory[j] === {DO_SIZE{1'b0}})
status[j] = 0;
else
status[j] = 1;
end
end
//----------------------------------------------------------------------------------------------------
//disable error messages option
initial
begin
pwrisa = PWRISA;
pwritim = PWRITIM;
tturbo = TTURBO;
ttmd = TTMD;
ttmd1 = TTMD1;
ttmd2 = TTMD2;
dis_err_msgs = 1'b1;
`ifdef S8FMLT_32K_SYS_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
//----------------------------------------------------------------------------------------------------
// print enable logic
assign print_enable = (dis_err_msgs === 1'b0) && (scan_mode !== 1'b1);
//----------------------------------------------------------------------------------------------------
// data out drive logic; depends on reset and the read operation (douti)
always @(read or posedge dreset or douti or negedge power_good or posedge reset_x)
begin
if ((power_good !==1)||(reset_x===1'b1))
begin
fm_do_reg <= {DO_SIZE{1'bx}};
end
else
begin
if (dreset === 1'b1)
begin
fm_do_reg <= {DO_SIZE{1'b0}};
end
else if (dreset === 1'b0)
begin
`ifdef functional
//add the delay when the functional macro is defind only
#(S8FMLT_32K_TAA-ACLK_DELAY);
`endif
fm_do_reg <= douti;
end
else
begin
fm_do_reg <= {DO_SIZE{1'bx}};
end
end
end
assign dout = (iso===1'b1)?(gnd_good?{DO_SIZE{1'b0}}:{DO_SIZE{1'bx}}):
(^iso===1'bx)?{DO_SIZE{1'bx}}:
(power_good===1'b0)?{DO_SIZE{1'bx}}:fm_do_reg;
//----------------------------------------------------------------------------------------------------
// power up sequence check for flash functionality
localparam PWR_OFF = 0;
localparam PWR_EN = 1;
localparam PWR_UP = 2;
localparam PWR_GOOD = 3;
wire power_up;
assign power_up = (vccd === 1'b1)&&(vpb_sw === 1'b1)&&(vpb === 1'b1)&&(vnb === 1'b0)&&(vgnd === 1'b0);
always @(power_up)
begin
if (power_up === 1'b1)
begin
pwr_up_time = $realtime;
flag_pd2topwr_error = 1'b1;
end
->pwr_up_trigger;
end
always @(pd1_int)
begin
if (pd1_int === 1'b0)
begin
pd1_down_time = $realtime;
flag_pd2topd1_error = 1'b0; // power-up sequence flag disabled due to pd1, pd2 repurpose
end
->pd1_trigger;
end
always @(pd2_int)
begin
if (pd2_int === 1'b0)
begin
pd2_down_time = $realtime;
flag_pd2topd1_error = 1'b0; // power-up sequence flag disabled due to pd1, pd2 repurpose
flag_pd2topwr_error = 1'b0; // power-up sequence flag disabled due to pd1, pd2 repurpose
end
->pd2_trigger;
end
always @(dreset)
begin
if (dreset === 1'b0)
begin
reset_down_time = $realtime;
end
->reset_trigger;
end
always @(pwr_up_trigger or pd1_trigger or pd2_trigger or reset_trigger) // always @(*) not used;make sure the always triggers after the time is sampled
begin
casex ({power_up,pd1_int,pd2_int,dreset})
4'b0xxx,4'b111x:
begin
power_state = PWR_OFF;
end
4'b101x,4'b110x:
begin
power_state = PWR_EN;
end
4'b1001:
begin
if (power_state != PWR_GOOD) // this could be a reset pulse during power good
begin
power_state = PWR_UP;
if ((pd2_down_time - pd1_down_time < S8FMLT_32K_TPWR))
begin
if ((print_enable)&&$time>0 &&(flag_pd2topd1_error===1'b1))
begin
$display ("===ERROR=== s8fmlt_32k_sys: Inrush current detected; pd2 to pd1 timing violated in %m @ %d",$time);
flag_pd2topd1_error = 1'b0; //disable the error message until the next pd2, pd1, or pwr_up smaple
end
end
if ((pd2_down_time - pwr_up_time< S8FMLT_32K_TPWR))
begin
if ((print_enable)&&$time>0 &&(flag_pd2topwr_error===1'b1))
begin
$display ("===ERROR=== s8fmlt_32k_sys: Inrush current detected; pd2 to vccd timing violated in %m @ %d",$time);
flag_pd2topwr_error = 1'b0; //disable the error message until the next pd2, pd1, or pwr_up smaple
end
end
end
end
4'b1000:
begin
power_state = PWR_UP;
if ((pd2_down_time - pd1_down_time < S8FMLT_32K_TPWR))
begin
if ((print_enable)&&$time>0 &&(flag_pd2topd1_error===1'b1))
begin
$display ("===ERROR=== s8fmlt_32k_sys: Inrush current detected; pd2 to pd1 timing violated in %m @ %d",$time);
flag_pd2topd1_error = 1'b0; //disable the error message until the next pd2, pd1, or pwr_up smaple
end
end
if ((pd2_down_time - pwr_up_time< S8FMLT_32K_TPWR))
begin
if ((print_enable)&&$time>0 &&(flag_pd2topwr_error===1'b1))
begin
$display ("===ERROR=== s8fmlt_32k_sys: Inrush current detected; pd2 to vccd timing violated in %m @ %d",$time);
flag_pd2topwr_error = 1'b0; //disable the error message until the next pd2, pd1, or pwr_up smaple
end
end
if (((reset_down_time - pd2_down_time)>=S8FMLT_32K_TRST)&&((reset_down_time - pd1_down_time)>=S8FMLT_32K_TRST))
begin
power_state = PWR_GOOD;
//r_clear_pages = 1; // create one page clear pulse.Does not affect external timing
//#1;
//r_clear_pages = 0;
end
end
default:
begin
power_state = PWR_EN;
end
endcase
end
assign power_good = (power_state === PWR_GOOD);
assign inhibit_pe = (power_state === PWR_OFF);
assign power_lv = (power_state === PWR_GOOD)||(power_state === PWR_UP);
//----------------------------------------------------------------------------------------------------
//sample sync inputs - wait for 0 hold time
always @(*) begin ax_d <= #ACLK_DELAY daxa; end
always @(*) begin ra_d <= #ACLK_DELAY dra; end
always @(*) begin ca_d <= #ACLK_DELAY dca; end
always @(*) begin mode_d <= #ACLK_DELAY dmode; end
always @(*) begin seq_d <= #ACLK_DELAY dseq; end
always @(*) begin di_d <= #ACLK_DELAY ddi; end
always @(*) begin pa_d <= #ACLK_DELAY dpa; end
always @(*) begin pw_d <= #ACLK_DELAY dpw; end
always @(*) begin tm_d <= #ACLK_DELAY dtm; end
always @(*) begin pnb_d <= #ACLK_DELAY dpnb; end
//----------------------------------------------------------------------------------------------------
// sample sync inputs with clk
always @(*) begin clk_delayed <= #S8FMLT_32K_TAW dclk;end // delay aclk by 4ns to account for the pulse with timing check notifier
always @(clk_delayed)
begin
if (clk_timing_error)
begin
clk_int = 1'b0;
if (print_enable)
begin
$display ("===ERROR=== s8fmlt_32k_sys: clk pulse width timing violation detected. This pulse will be ignored in %m @ %d",$time);
end
end
else
begin
clk_int = clk_delayed;
end
end
always @(posedge clk_int or posedge dreset or posedge reset_hv or posedge reset_x)
begin
if (dreset === 1'b1)
begin
address <= {ADDR_BITS{1'b0}};
read_address <= {ADDR_BITS{1'b0}};
mode_l <= {MODE_SIZE{1'b0}};
seq_l <= {SEQ_SIZE{1'b0}};
prev_mode <= {MODE_SIZE{1'b0}};
prev_seq <= {SEQ_SIZE{1'b0}};
pa_l <= {PADDR_BITS{1'b0}};
di_l <= {DI_SIZE{1'b0}};
pw_l <= 1'b0;
tm_l <= {TADDR_BITS{1'b0}};
ra_l <= {(RADDR_BITS+AADDR_BITS){1'b0}};
//reset flags and latches
preprg_flag <= 1'b0;
pwrall_flag <= 1'b0;
page_clr_flag <= 1'b0;
page_corrupt_flag <= 1'b0;
margin_exit_error <= 1'b0;
pnb_l <= 1'b0;
end
else if ((^dreset === 1'bx)||(reset_x===1'b1))
begin
address <= {ADDR_BITS{1'bx}};
read_address <= {ADDR_BITS{1'bx}};
mode_l <= {MODE_SIZE{1'bx}};
seq_l <= {SEQ_SIZE{1'bx}};
prev_mode <= {MODE_SIZE{1'bx}};
prev_seq <= {SEQ_SIZE{1'bx}};
pa_l <= {PADDR_BITS{1'bx}};
di_l <= {DI_SIZE{1'bx}};
pw_l <= 1'bx;
tm_l <= {TADDR_BITS{1'bx}};
ra_l <= {(RADDR_BITS+AADDR_BITS){1'bx}};
//reset flags and latches
preprg_flag <= 1'bx;
pwrall_flag <= 1'bx;
page_clr_flag <= 1'bx;
page_corrupt_flag <= 1'bx;
pnb_l <= 1'bx;
end
else if (reset_hv === 1'b1)
begin
prev_mode <= {MODE_SIZE{1'b0}};
prev_seq <= {SEQ_SIZE{1'b0}};
mode_l <= {MODE_SIZE{1'b0}};
seq_l <= {SEQ_SIZE{1'b0}};
end
else
begin
address <= {ax_d,ra_d,ca_d};
prev_mode <= mode_l;
prev_seq <= seq_l;
mode_l <= mode_d;
seq_l <= seq_d;
pa_l <= pa_d;
di_l <= di_d;
pw_l <= pw_d;
tm_l <= tm_d;
ra_l <= {ax_d,ra_d};
pnb_l <= pnb_d;
#0.1;
if (pd2orsleep === 1'b0)
begin
->run_mode; // start executin operations only when not in sleep
end
end
end
//----------------------------------------------------------------------------------------------------
// Reset based in seq 0
always @(*)
begin
if (seq_l === 2'b00)
begin
ers_pe_in_seq2 = 1'b0; // clear pe error at the end of erase
prg_pe_in_seq2 = 1'b0; // clear pe error at the end of program
reset_pump_timing_error = 1'b1; // create a reset pulse for the pump timing error
#1;
reset_pump_timing_error = 1'b0;
end
end
//----------------------------------------------------------------------------------------------------
// program mode detect
assign program_mode = (mode_l === PRG_WL)||(mode_l === PRG_SC)||(mode_l === PRG_BK)||(mode_l === PRG_BK_ALL);
//----------------------------------------------------------------------------------------------------
// Write data into page latches
always @(run_mode or
posedge dreset or
page_clr_flag or
page_corrupt_flag or
negedge power_lv or
posedge reset_x )
begin
//check for z in data in
for (j=0;j<DI_SIZE;j=j+1)
begin
if (di_l[j] === 1'bz)
begin
di_l[j] = 1'bx;
end
end
//Start page write
if ((power_lv !== 1'b1) || (page_corrupt_flag === 1'b1) || (reset_x === 1'b1))
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
else // power good
begin
if (dreset === 1'b1)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'b0}};
end
end
else if (dreset === 1'b0)
begin
if (page_clr_flag === 1'b1)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'b0}};
end
end
else if (page_clr_flag === 1'b0)
begin
if (pw_l === 1'b1)
begin
if (pwrall_flag === 1'b1)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]=di_l;
end
end
else if (pwrall_flag === 1'b0)
begin
if (^pa_l !== 1'bx)
begin
page_latch[pa_l] = di_l;
end
else // page address is valid
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
else // pwrall_flag not valid
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
else if (^pw_l === 1'bx)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
else // page_clr_flag latches not valid
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
//check pw timing error
if (pw_timing_error)
begin
if ((!pa_timing_error)&&(!pwrall_flag))
begin
page_latch[pa_l] = {DI_SIZE{1'bx}};
end
else
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
if (di_timing_error && pw_l)
begin
if (pwrall_flag)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
else
begin
page_latch[pa_l] = {DI_SIZE{1'bx}};
end
end
if (pa_timing_error && pw_l)
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
else // reset not valid
begin
for(j=0;j<PAGE_SIZE;j=j+1)
begin
page_latch[j]={DI_SIZE{1'bx}};
end
end
end
end
//-------------------------------------------------------------------------------------------
// mode decoding
always @(run_mode or pe) //or mode_l or seq_l
begin
page_clr_flag = 1'b0;
page_corrupt_flag = 1'b0;
if (dreset === 1'b0 && pd2orsleep === 1'b0 && scan_mode === 1'b0)
begin
if (mode_timing_error)
begin
if (print_enable) begin $display("===ERROR=== s8fmlt_32k_sys: mode ignored due to mode timing error in %m @ %d",$time); end
page_corrupt_flag = 1'b1; // trigger the write always block
read_memory; // call the read task to signal with x whent the mode is corrupted
-> read; //start the read operation witn the corrupted memory output
end
else
begin
case (mode_l)
READ:
begin
read_address = address;
read_memory; //updates memory output (douti)
-> read; //start the read operation with the new memroy output
-> reset_dummy_read_event;
end
PREPRG:
begin
set_preprg_flag;
end
PWRALL:
begin
set_pwrall_flag;
end
PS_IDLE:
begin
// idle operation; No mode operation; Used for write only operations
end
RSTHV :
begin
gen_reset_hv;
end
CLR_PAGE:
begin
set_pageclr_flag;
end
ERS_WL:
begin
erase_wl(address);
end
ERS_BK:
begin
erase_bk(address);
end
PRG_WL:
begin
program_wl(address);
end
PRG_BK:
begin
program_bk(address);
end
PRG_BK_ALL:
begin
program_bk_all(address);
end
default: // there are valid unused modes when the macro should do "nothing"
begin
if (^mode_l === 1'bx)
begin
page_corrupt_flag = 1'b1; // trigger the write always block
read_memory; // call the read task to signal with x whent the mode is corrupted
-> read; //start the read operation witn the corrupted memory output
end
end
endcase
prev_seq_sample = seq_sample;
end
end
end
//---------------------------------------------------------------------------------------
// Test mode decoding for tm[4:0]
assign amuxbusa = (iso===1'b1)?((power_down_amux===1'b1)?1'bz:1'bx):
(^iso===1'bx)?1'bx:
(power_good===1'b0)?1'bx:amuxbusa_int;
assign amuxbusb = (iso===1'b1)?((power_down_amux===1'b1)?1'bz:1'bx):
(^iso===1'bx)?1'bx:
(power_good===1'b0)?1'bx:amuxbusb_int;
assign VMARG_AUX = (p_up_analog === 1'b1)? VMARG_AUX_int:1'bx;
always @(*)
begin
amuxbusa_int = 1'bz;
amuxbusb_int = 1'bz;
tm_en_nvl = 1'b0;
tm_vmarg = 1'b0;
tm_enpos = 1'b0;
tm_enneg = 1'b0;
tm_rdhvpl = 1'b0;
tm_xydec = 1'b0;
tm_disrow = 1'b0;
tm_encol = 1'b0;
tm_isa = 1'b0;
tm_itim = 1'b0;
tm_en_vctat = 1'b0;
if (^tm_l===1'bx || tm_timing_error === 1'b1 || ^scan_mode===1'bx)
begin
amuxbusa_int = 1'bx;
amuxbusb_int = 1'bx;
tm_en_nvl = 1'bx;
tm_vmarg = 1'bx;
tm_enpos = 1'bx;
tm_enneg = 1'bx;
tm_rdhvpl = 1'bx;
tm_xydec = 1'bx;
tm_disrow = 1'bx;
tm_encol = 1'bx;
tm_isa = 1'bx;
tm_itim = 1'bx;
tm_en_vctat = 1'bx;
end
else if (scan_mode === 1'b0)
begin
case (tm_l)
5'd1:
begin
//tm_enpos = 1'b1;
//tm_enneg = 1'b1;
amuxbusa_int = VPOS;
amuxbusb_int = ~VNEG;
end
5'd2:
begin
if (pnb_l === 1'b1)
begin
tm_enpos = 1'b1; // enable positive pump
tm_vmarg = 1'b1; // enable mdac
amuxbusa_int = vmarg;
end
else if (pnb_l === 1'b0)
begin
//do nothing let amuxbus pins floating
end
else //margin mode has been set correctly but pnb is not clean
begin
amuxbusa_int = 1'bx;
amuxbusb_int = 1'bx;
end
end
5'd4:
begin
tm_vmarg = 1'b1; //enable mdac
if (pnb_l === 1'b1)
begin
tm_enpos = 1'b1; // enable positive pump
end
else if (pnb_l === 1'b0)
begin
tm_enneg = 1'b1; // enable negative pump
end
else //pnb dirty
begin
tm_enpos = 1'bx;
tm_enneg = 1'bx;
end
end
5'd5:
begin
tm_vmarg = 1'b1;
tm_isa = 1'b1;
tm_itim = 1'b1;
if (pnb_l === 1'b1)
begin
tm_enpos = 1'b1; // enable positive pump
end
else if (pnb_l === 1'b0)
begin
tm_enpos = 1'b1; // enable positive pump
tm_enneg = 1'b1; // enable negative pump
end
else //pnb dirty
begin
tm_enpos = 1'bx;
tm_enneg = 1'bx;
end
end
5'd6:
begin
tm_vmarg = 1'b1; // enable mdac
if (pnb_l === 1'b1)
begin
tm_enpos = 1'b1; // enable positive pump
amuxbusa_int = VPOS;
end
else if (pnb_l === 1'b0)
begin
tm_enpos = 1'b1; // enable positive pump
tm_enneg = 1'b1; // enable negative pump
amuxbusb_int = ~VNEG;
end
else //pnb dirty
begin
tm_enpos = 1'bx;
tm_enneg = 1'bx;
amuxbusa_int = 1'bx;
amuxbusb_int = 1'bx;
end
end
5'd7:
begin
tm_en_nvl = 1'b1;
if (pnb_l === 1'b1)
begin
tm_enpos = 1'b1; // enable positive pump
end
else if (pnb_l === 1'b0)
begin
tm_enneg = 1'b1; // enable negative pump
end
else //pnb dirty
begin
tm_enpos = 1'bx;
tm_enneg = 1'bx;
end
end
5'd8:
begin
amuxbusa_int = 1'b1;//isamon
amuxbusb_int = 1'b1;//itimmon
end
5'd9:
begin
tm_isa = 1'b1;
amuxbusb_int = 1'b1;//itimmon
end
5'd10:
begin
amuxbusa_int = 1'b1;//isamon
tm_itim = 1'b1;
end
5'd11:
begin
tm_isa = 1'b1;
tm_itim = 1'b1;
end
5'd13:
begin
tm_enpos = 1'b1;
amuxbusa_int = 1'b1;//isamon
amuxbusb_int = 1'b1;//itimmon
end
5'd16:
begin
tm_en_vctat = 1'b1; // enable vctat
tm_enpos = 1'b0;
amuxbusa_int = vref;//vref is an input, just pass it out does not depend on refsel
amuxbusb_int = vctat;//vctat is an internal wire NOTE - need to implement logic for when valid
end
5'd17://regular reads
begin
tm_en_vctat = 1'b1; //enable vctat to generate v700 and v1400
tm_enpos = 1'b1;
amuxbusa_int = vctat;//v700 - same logic as vctat
amuxbusb_int = vctat;//v1400 - same logic as vctat
end
5'd18://extreme timing reads - NOTE maybe need to add etrm_tim
begin
//amuxbusa_int = vbl;
tm_enpos = 1'b1;
amuxbusa_int = vlim;//v2
amuxbusb_int = vlim;
end
5'd19:
begin
tm_enpos = 1'b1;
amuxbusa_int = vbl;
end
5'd20:
begin
amuxbusa_int = iref;// is an input, just pass it out
end
5'd21:
begin
tm_enpos = 1'b1;
amuxbusb_int = iref;// NOTE add logic from iref if needed
end
5'd22:
begin
amuxbusa_int = vbl;
end
5'd24:
begin
tm_rdhvpl = 1'b1;
tm_disrow = 1'b1;
end
5'd25:
begin
tm_xydec = 1'b1;
end
5'd26:
begin
tm_xydec = 1'b1;
tm_disrow = 1'b1;
end
5'd27:
begin
tm_xydec = 1'b1;
tm_encol = 1'b1;
end
default:
begin
end
endcase
end
end
//--------------------------------------------------------------------------------------
// Read task
task read_memory(); // implement display switch based on the error (e.g. if power is bad disable the rest of the error messages)
reg read_x;
begin
read_x = 1'b0;
if (!power_good)
begin
if (print_enable && (dummy_read_flag!==1'b1)) $display("===ERROR=== s8fmlt_32k_sys: Design not powered during read in %m @ %d",$time);
read_x=1'b1;
end
if (dummy_read_flag===1'b1)
begin
if (print_enable &&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: Dummy Read in Margin Mode detected in %m @ %d",$time);
end
if (^mode_l === 1'bx)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Received corrupted mode data in %m @ %d",$time);
read_x=1'b1;
end
if (read_isa !== 1'b1)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: isa not active in %m @ %d",$time);
read_x=1'b1;
end
if (read_itim !== 1'b1)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: itim not active in %m @ %d",$time);
read_x=1'b1;
end
if (seq_l !== 2'b00)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Read mode with sequence %d in %m @ %d",seq_l,$time);
read_x=1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during read %d in %m @ %d",seq_l,$time);
read_x=1'b1;
end
if (tm_vmarg===1'b1&&(^pnb_l === 1'bx))
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Margin mode read with pnb - %b in %m @ %d",pnb_l,$time);
read_x=1'b1;
end
if (tm_vmarg===1'b1&&(pnb_timing_error === 1'bx))
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Pnb timing violation during margin mode - %b in %m @ %d",pnb_l,$time);
read_x=1'b1;
end
if (tm_vmarg===1'b1&&(vmarg !== 1'b1))
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Margin mode read with VMARG. Check mdac bus - %b in %m @ %d",vmarg,$time);
read_x=1'b1;
end
if (tm_vmarg===1'b1&&(ra_ttmd1 === 1'b1))
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: ttmd1 not expired after change in the row address in %m @ %d",vmarg,$time);
read_x=1'b1;
end
if (mdac_off_x === 1'b1)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Read violating ttmd2 delay time after margin mode in %m @ %d",$time);
read_x=1'b1;
end
if (^dturbo_b === 1'bx)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Invalid turbo_b during read in %m @ %d",$time);
read_x=1'b1;
end
// if (wait_for_turbo_b !== 1'b0)
// begin
// if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Turbo_b was not 0 for %d after idac/sdac trim change or return to active mode in %m @ %d", tturbo,$time);
// read_x=1'b1;
// end
if (busy)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode changed to read during HV operation in %m @ %d",$time);
read_x=1'b1;
end
if (tbb_timing_error)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to turbo_b timing violation in %m @ %d",$time);
read_x=1'b1;
end
if (addr_timing_error)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to address timing violation in %m @ %d",$time);
read_x=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to iso tactive2 timing violation in %m @ %d",$time);
read_x=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to rst to clk timing violation in %m @ %d",$time);
read_x=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to pd2 tactive timing violation in %m @ %d",$time);
read_x=1'b1;
end
if (^address===1'bx)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read error due to invalid address in %m @ %d",$time);
read_x=1'b1;
end
if ((^tm_l === 1'bx)||(tm_timing_error === 1'b1))
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: tm bus is not valid (%b) in %m @ %d",tm_l,$time);
read_x = 1'b1;
end
if (margin_exit_error === 1'b1)
begin
if ((print_enable && (dummy_read_flag!==1'b1))&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: read corrupt due to incorrect margin mode exit in %m @ %d",$time);
read_x = 1'b1;
end
if (pd2orsleep !== 1'b0)
begin
read_x = 1'b1;
end
// check for special row address
if(read_address[ADDR_BITS-1] === 1'b1)
begin
read_address[ADDR_BITS-2:CADDR_BITS+SRADDR_BITS] ={(ADDR_BITS-2-CADDR_BITS-SRADDR_BITS+1){1'b0}};
end
if(read_x)
begin
douti = {DO_SIZE{1'bx}};
end
else if (tm_rdhvpl)
begin
douti =~{page_latch[{address[CADDR_BITS-1:0],3'b111}],
page_latch[{address[CADDR_BITS-1:0],3'b110}],
page_latch[{address[CADDR_BITS-1:0],3'b101}],
page_latch[{address[CADDR_BITS-1:0],3'b100}],
page_latch[{address[CADDR_BITS-1:0],3'b011}],
page_latch[{address[CADDR_BITS-1:0],3'b010}],
page_latch[{address[CADDR_BITS-1:0],3'b001}],
page_latch[{address[CADDR_BITS-1:0],3'b000}]};
end //read hvpl is asynchronous and uses the page address.
else if (tm_disrow)
begin
douti = {DO_SIZE{1'b1}};
end
else
begin
// if (read_address [ADDR_BITS-3:ADDR_BITS-4] === 2'b11)
// begin
// douti = {DO_SIZE{1'b1}};
// end
// else
begin
douti = memory[read_address];
end
end
end
endtask
// preprogram set task
task set_preprg_flag();
reg preprg_x;
begin
preprg_x = 1'b0;
if (!power_good)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: Design not powered during preprogram in %m @ %d",$time);
preprg_x=1'b1;
end
if (busy)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode changed to preprogram during HV operation in %m @ %d",$time);
preprg_x=1'b1;
end
if (seq_l != 2'b00)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Preprogram mode with sequence %d in %m @ %d",seq_l, $time);
preprg_x=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Preprogram error due to iso tactive2 timing violation in %m @ %d",$time);
preprg_x=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Preprogram error due to rst to clk timing violation in %m @ %d",$time);
preprg_x=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Preprogram error due to pd2 tactive timing violation in %m @ %d",$time);
preprg_x=1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during preprogram %d in %m @ %d",seq_l,$time);
preprg_x=1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: Preprogram mode detected during sleep - ignored in %m @ %d",$time);
preprg_x = 1'b1;
end
// if (clk_timing_error)
// begin
// if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Pre-program error due to clk timing violation in %m @ %d",$time);
// preprg_x=1'b1;
// end
if (preprg_x === 1'b0)
begin
preprg_flag = 1'b1;
end
else
begin
preprg_flag = 1'bx;
end
end
endtask
//page write all mode set task
task set_pwrall_flag();
reg pwrall_x;
begin
pwrall_x = 1'b0;
if (!power_good)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: Design not powered during page write all in %m @ %d",$time);
pwrall_x=1'b1;
end
if (busy)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode changed to page write all during HV operation in %m @ %d",$time);
pwrall_x=1'b1;
end
if (seq_l != 2'b00)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: page write all mode without sequence 0 in %m @ %d",$time);
pwrall_x=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: page write all error due to iso tactive2 timing violation in %m @ %d",$time);
pwrall_x=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: page write all error due to rst to clk timing violation in %m @ %d",$time);
pwrall_x=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: page write all error due to pd2 tactive timing violation in %m @ %d",$time);
pwrall_x=1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during set page write all %d in %m @ %d",seq_l,$time);
pwrall_x=1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: Page write all mode detected during sleep - ignored in %m @ %d",$time);
pwrall_x = 1'b1;
end
// if (clk_timing_error)
// begin
// if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Page write all flag error due to clk timing violation in %m @ %d",$time);
// pwrall_x=1'b1;
// end
if (pwrall_x === 1'b0)
begin
pwrall_flag = 1'b1;
end
else
begin
pwrall_flag = 1'bx;
end
end
endtask
//page clear mode set task
task set_pageclr_flag();
reg pageclr_x;
begin
pageclr_x = 1'b0;
if (!power_good)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: Design not powered during clear page latches mode in %m @ %d",$time);
pageclr_x=1'b1;
end
if (busy)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode changed to clear page latches during HV operation in %m @ %d",$time);
pageclr_x=1'b1;
end
if (seq_l != 2'b00)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: clear page latches mode without sequence 0 in %m @ %d",$time);
pageclr_x=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: clear page latches mode error due to iso tactive2 timing violation in %m @ %d",$time);
pageclr_x=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: clear page latches mode error due to rst to clk timing violation in %m @ %d",$time);
pageclr_x=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: clear page latches mode error due to pd2 tactive timing violation in %m @ %d",$time);
pageclr_x=1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during page reset %d in %m @ %d",seq_l,$time);
pageclr_x=1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: clear page latches mode detected during sleep - ignored in %m @ %d",$time);
pageclr_x = 1'b1;
end
// if (clk_timing_error)
// begin
// if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: clear page latches flag error due to clk timing violation in %m @ %d",$time);
// pageclr_x=1'b1;
// end
if (pageclr_x === 1'b0)
begin
page_clr_flag = 1'b1;
end
else
begin
page_clr_flag = 1'bx;
end
end
endtask
//generate reset hv pulse
task gen_reset_hv();
reg reset_hv_x;
begin
reset_hv_x = 1'b0;
if (!power_good)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: Design not powered during clear page latches mode in %m @ %d",$time);
reset_hv_x=1'b1;
end
if (seq_l != 2'b00)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: reset hv mode without sequence 0 in %m @ %d",$time);
reset_hv_x=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: reset hv mode error due to iso tactive2 timing violation in %m @ %d",$time);
reset_hv_x=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: reset hv mode error due to rst to clk timing violation in %m @ %d",$time);
reset_hv_x=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: reset hv mode error due to pd2 tactive timing violation in %m @ %d",$time);
reset_hv_x=1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during page reset %d in %m @ %d",seq_l,$time);
reset_hv_x=1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: clear page latches mode detected during sleep - ignored in %m @ %d",$time);
reset_hv_x = 1'b1;
end
if (reset_hv_x === 1'b0)
begin
margin_exit_error = 1'b0;
reset_hv = 1'b1;
#1;
reset_hv = 1'b0;
end
else
begin
reset_hv = 1'bx;
end
end
endtask
// check sequence task; called duting hv operations
task check_sequence ();
begin
sequence_good = 1'b0;
case (seq_l)
2'd0:
begin
if ((prev_seq === 2'd0)||(prev_seq === 2'd3))
begin
sequence_good = 1'b1;
end
end
2'd1:
begin
busy = 1'b1;
if ((prev_seq === 2'd1)||(prev_seq === 2'd0))
begin
sequence_good = 1'b1;
end
end
2'd2:
begin
if ((prev_seq === 2'd2)||(prev_seq === 2'd1))
begin
sequence_good = 1'b1;
end
end
2'd3:
begin
busy = 1'b0;
if (program_mode === 1'b1)
begin
preprg_flag = 1'b0;
pwrall_flag = 1'b0;
end
if (margin_exit_error === 1'b1)
begin
if ((prev_seq === 2'd3)||(prev_seq === 2'd1))
begin
sequence_good = 1'b1;
end
margin_exit_error = 1'b0;
reset_hv = 1'b1;
#1;
reset_hv = 1'b0;
end
if ((prev_seq === 2'd3)||(prev_seq === 2'd2))
begin
sequence_good = 1'b1;
end
end
default:
begin
sequence_good = 1'b0;
end
endcase
if (prev_seq !== seq_l)
begin //different sequence clocked in
seq_sample = $realtime;
case (prev_seq)
2'd0:
begin
if ((seq_sample - prev_seq_sample) < S8FMLT_32K_TCY-0.1)
begin
sequence_good = 1'b0;
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence 0 lasted for %d; less than TCY (%d) in %m @ %d",$realtime - prev_seq_sample,S8FMLT_32K_TCY,$time);
end
end
2'd1:
begin
if ((seq_sample - prev_seq_sample) < S8FMLT_32K_TS1-0.1)
begin
sequence_good = 1'b0;
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence 1 lasted for %d; less than TS1 (%d) in %m @ %d",$realtime - prev_seq_sample,S8FMLT_32K_TS1,$time);
end
end
2'd2:
begin
//covered in specify block;includes timings to pe as well
end
2'd3:
begin
if ((seq_sample - prev_seq_sample) < S8FMLT_32K_TS3-0.15)
begin
sequence_good = 1'b0;
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence 3 lasted for %d; less than TS3 (%d) in %m @ %d",$realtime - prev_seq_sample,S8FMLT_32K_TS3,$time);
end
end
default:
begin
end
endcase
end
if (seq_l > 1)
begin
if (mode_l === prev_mode)
begin
mode_good = 1'b1;
end
else
begin
mode_good = 1'b0;
end
end
end
endtask
task erase_wl;
//parameter ADDR_BITS = 14;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] erase_addr;
//reg [ADDR_BITS-1:0] i;
integer i;
reg erase_wl_x;
reg erase_x_all;
//reg ers_pe_in_seq2;
begin
//verify the running conditions
check_sequence; // updates the sequence good flag
if(seq_l === 2'b01) //reset the error bit in seq1 - begining of the erase operation
begin
erase_wl_x = 1'b0;
pe_timing_error = 1'b0;
erase_x_all = 1'b0;
end
if(!power_good && !inhibit_pe)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: model not powered during erase in %m @ %d",$time);
erase_wl_x = 1'b1;
end
if (!sequence_good)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence %d after Sequence %d, in erase mode in %m @ %d",seq_l,prev_seq,$time);
erase_wl_x = 1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during erase %d in %m @ %d",seq_l,$time);
erase_wl_x=1'b1;
end
if (!mode_good)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode change during erase operation - %h -> %h in %m @ %d",prev_mode,mode_l,$time);
erase_wl_x = 1'b1;
end
if (preprg_flag)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase with preprogram flag set in %m @ %d",$time);
erase_wl_x = 1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: Erase mode during sleep in %m @ %d",$time);
end
// if (clk_timing_error)
// begin
// if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase error due to clk timing violation in %m @ %d",$time);
// erase_wl_x=1'b1;
// end
if (addr_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase error due to ADDRESS timing violation in %m @ %d",$time);
erase_x_all=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase error due to iso tactive1 timing violation in %m @ %d",$time);
erase_x_all=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase error due to rst to aclkt timing violation in %m @ %d",$time);
erase_x_all=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase error due to pd2 tactive timing violation in %m @ %d",$time);
erase_x_all=1'b1;
end
if (^addr === 1'bx)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase with invalid address in %m @ %d",$time);
erase_x_all=1'b1;
end
if (margin_exit_error === 1'b1 && seq_l === 2'b10)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase corrupt due to incorrect margin mode exit in %m @ %d",$time);
erase_wl_x = 1'b1;
end
if (ers_prg_hv_error)
begin
if ((print_enable)&&(power_good))
begin
$display("===ERROR=== s8fmlt_32k_sys: HV voltages are not clean during the entire erase operation in %m @ %d",$time);
hv_good_report;
end
erase_wl_x = 1'b1;
end
erase_addr = {ADDR_BITS{1'b0}};
erase_addr[ADDR_BITS-1:CADDR_BITS]=addr[ADDR_BITS-1:CADDR_BITS];//trim the input address to ignore CA address
if(erase_addr[ADDR_BITS-1] === 1'b1)
begin
erase_addr[ADDR_BITS-2:CADDR_BITS+SRADDR_BITS] ={(BADDR_BITS-PLADDR_BITS+RADDR_BITS-SRADDR_BITS){1'b0}};
end
if ((!pd2orsleep) && (!inhibit_pe) && (erase_x_all === 1'b0))
begin
case ({pe,seq_l})
3'b000://sequece 0 pe 0
begin
ers_pe_in_seq2 = 1'b0;
end
3'b001://sequence 1 pe 0
begin
end
3'b010://sequence 2 pe 0
begin
end
3'b110://sequence 2 pe 1
begin // erase cicle - set to x at the begining of erase
ers_pe_in_seq2 = 1'b1;
for(i=0;i<COLUMNS;i=i+1)
begin
memory[erase_addr+i]= {DO_SIZE{1'bx}};
status[erase_addr+i]= 1'b1;
end
end
3'b011://sequence 3 pe 0
begin
if (ers_pe_in_seq2 === 1'b1)
begin
if(pe_timing_error === 1'b0)
begin
for(i=0;i<COLUMNS;i=i+1)
begin
if(erase_wl_x === 1'b0)
begin
memory[erase_addr+i]= {DO_SIZE{1'b0}};
status[erase_addr+i]= 1'b0;
end
else
begin
memory[erase_addr+i]= {DO_SIZE{1'bx}};
status[erase_addr+i]= 1'b1; // memory location still requires a clean program
end
end
end
else
begin //timing error; corrupt hv operation
$display("===ERROR=== s8fmlt_32k_sys: Memory location corrupted due to pe timing violation in %m @ %d",pe,seq_l,$time);
for(i=0;i<COLUMNS;i=i+1)
begin
memory[erase_addr+i]= {DO_SIZE{1'bx}};
status[erase_addr+i]= 1'b1;
end
end
end
//ers_pe_in_seq2 = 1'b0;
end
default:
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Pe is %b in sequence %d in %m @ %d",pe,seq_l,$time);
end
endcase
end
if (erase_x_all === 1'b1)
begin
$display("===ERROR=== s8fmlt_32k_sys: Corrupting entire memory due to invalid address in %m @ %d",$time);
for(j = 0;j < MEM_SIZE;j = j + 1)
begin
memory[j] = {DO_SIZE{1'bx}};
status[j] = 1;
end
end
end
endtask
// program row task
task program_wl;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] program_addr;
integer i;
reg program_wl_x;
reg [CADDR_BITS-1:0] page_addr;
reg [COLUMNS-1:0] status_error;
reg prg_x_all;
//reg prg_pe_in_seq2;
reg program_ones;
begin
//verify the running conditions
check_sequence; // updates the sequence good flag
if(seq_l === 2'b01) //reset the error bit in seq1 - begining of the program operation
begin
program_wl_x = 1'b0;
pe_timing_error = 1'b0;
prg_x_all=1'b0;
end
if(!power_good && !inhibit_pe)
begin
if (print_enable) $display("===ERROR=== s8fmlt_32k_sys: model not powered during program in %m @ %d",$time);
program_wl_x = 1'b1;
end
if (!sequence_good)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence %d after Sequence %d, in program mode @%d",seq_l,prev_seq,$time);
program_wl_x = 1'b1;
end
if (seq_timing_error === 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Sequence timing violation during program %d in %m @ %d",seq_l,$time);
program_wl_x=1'b1;
end
if (!mode_good)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Mode change during program operation - %h -> %h in %m @ %d",prev_mode,mode_l, $time);
program_wl_x = 1'b1;
end
if (vbl !== 1'b1)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Vbl voltage not active during program operation. Check bdac in %m @ %d",$time,);
program_wl_x = 1'b1;
end
if (pd2orsleep)
begin
if ((print_enable)&&(power_good)) $display("===WARNING=== s8fmlt_32k_sys: Program mode during sleep in %m @ %d",$time);
end
// if (clk_timing_error)
// begin
// if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program error due to clk timing violation in %m @ %d",$time);
// program_wl_x=1'b1;
// end
if (addr_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program error due to address timing violation in %m @ %d",$time);
prg_x_all=1'b1;
end
if (iso_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program error due to iso tactive1 timing violation in %m @ %d",$time);
prg_x_all=1'b1;
end
if (rst_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program error due to rst to aclk timing violation in %m @ %d",$time);
prg_x_all=1'b1;
end
if (pd2_timing_error)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program error due to pd2 tactive timing violation in %m @ %d",$time);
prg_x_all=1'b1;
end
if (^addr === 1'bx)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Erase with invalid address in %m @ %d",$time);
prg_x_all=1'b1;
end
if (margin_exit_error === 1'b1 && seq_l === 2'b10 )
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: Program corrupt due to incorrect margin mode exit in %m @ %d",$time);
program_wl_x = 1'b1;
end
if (ers_prg_hv_error)
begin
if ((print_enable)&&(power_good))
begin
$display("===ERROR=== s8fmlt_32k_sys: Incorrect VPOS/VNEG drive during program in %m @ %d",$time);
hv_good_report;
end
program_wl_x = 1'b1;
end
program_addr = {ADDR_BITS{1'b0}};
program_addr[ADDR_BITS-1:CADDR_BITS]=addr[ADDR_BITS-1:CADDR_BITS];//trim the input address to ignore CA address
if(program_addr[ADDR_BITS-1] === 1'b1)
begin
program_addr[ADDR_BITS-2:CADDR_BITS+SRADDR_BITS] = {(BADDR_BITS-PLADDR_BITS+RADDR_BITS-SRADDR_BITS){1'b0}};
end
if ((!pd2orsleep) && (!inhibit_pe)&&(prg_x_all===1'b0))
begin
case ({pe,seq_l})
3'b000://sequece 0 pe 0
begin
prg_pe_in_seq2 = 1'b0;
end
3'b001://sequence 1 pe 0
begin
end
3'b010://sequence 2 pe 0
begin
end
3'b110://sequence 2 pe 1
begin
program_ones = preprg_flag;
prg_pe_in_seq2 = 1'b1;
for(i=0;i<COLUMNS;i=i+1)
begin
if (status[program_addr+i] === 1'b1 && preprg_flag === 1'b0)
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: program on un-erased memory location %h in %m @ %d",program_addr+i,$time);
re_program[program_addr+i]= 1'b1;
end
memory[program_addr+i]= {DO_SIZE{1'bx}};
//#0.01;
status[program_addr+i]= 1'b1;
end
end
3'b011://sequence 3 pe 0
begin
if (prg_pe_in_seq2 === 1'b1)
begin
if(pe_timing_error === 1'b0)
begin
for(i=0;i<COLUMNS;i=i+1)
begin
if(program_wl_x === 1'b0)
begin
if (program_ones === 1'b1)
begin // do preprogram
memory[program_addr+i]= {DO_SIZE{1'b1}};
status[program_addr+i]= 1'b1;
end
else if (program_ones === 1'b0)
begin
if (re_program[program_addr+i]!== 1'b1)
begin
page_addr = i;
memory[program_addr+i]= {page_latch[{page_addr,3'b111}],
page_latch[{page_addr,3'b110}],
page_latch[{page_addr,3'b101}],
page_latch[{page_addr,3'b100}],
page_latch[{page_addr,3'b011}],
page_latch[{page_addr,3'b010}],
page_latch[{page_addr,3'b001}],
page_latch[{page_addr,3'b000}]};
end
end
else
begin
memory[program_addr+i]= {DO_SIZE{1'bx}};
status[program_addr+i]= 1'b1;
end
end
else
begin
memory[program_addr+i]= {DO_SIZE{1'bx}};
status[program_addr+i]= 1'b1; // memory location still requires a clean program
end
end
end
else
begin //timing error; corrupt hv operation
$display("===ERROR=== s8fmlt_32k_sys: Memory location corrupted due to pe timing violation in %m @ %d",pe,seq_l,$time);
for(i=0;i<COLUMNS;i=i+1)
begin
memory[program_addr+i]= {DO_SIZE{1'bx}};
status[program_addr+i]= 1'b1;
end
end
end
//prg_pe_in_seq2 = 1'b0;
end
default:
begin
if ((print_enable)&&(power_good)) $display("===ERROR=== s8fmlt_32k_sys: pe is %b in sequence %d in %m @ %d",pe,seq_l,$time);
end
endcase
end
if (prg_x_all === 1'b1)
begin
$display("===ERROR=== s8fmlt_32k_sys: Corrupting entire memory due to invalid address in %m @ %d",$time);
for(j = 0;j < MEM_SIZE;j = j + 1)
begin
memory[j] = {DO_SIZE{1'bx}};
status[j] = 1;
end
end
end
endtask
task erase_sc;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] erase_sc_addr;
integer k;
begin
erase_sc_addr = {ADDR_BITS{1'b0}};
erase_sc_addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS]=addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS];
if (erase_sc_addr[ADDR_BITS-1] === 1'b0)
begin
for(k=0;k<SECTOR_ROWS;k=k+1)
begin
erase_wl(erase_sc_addr);
erase_sc_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]=erase_sc_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]+1;
end
end
else if (erase_sc_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Erase Sector in special rows is not allowed. Executing Erase WL in %m @ %d",$time);
end
//call erase wl for the input address when ax = 1
erase_wl(addr);
end
end
endtask
task erase_bk;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] erase_bk_addr;
integer k;
begin
erase_bk_addr = {ADDR_BITS{1'b0}};
erase_bk_addr[ADDR_BITS-1]=addr[ADDR_BITS-1];
if (erase_bk_addr[ADDR_BITS-1] === 1'b0)
begin
erase_sc(erase_bk_addr);
/*
for(k=0;k<SECTORS;k=k+1)
begin
erase_sc(erase_bk_addr);
erase_bk_addr[BADDR_BITS+RADDR_BITS+CADDR_BITS-1:RADDR_BITS+CADDR_BITS]=erase_bk_addr[BADDR_BITS+RADDR_BITS+CADDR_BITS-1:RADDR_BITS+CADDR_BITS]+1;
end
*/
end
else if (erase_bk_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Erase Bulk in special rows is not allowed. Executing Erase WL in %m @ %d",$time);
end
//call erase wl for the input address when ax = 1
erase_wl(addr);
end
end
endtask
task program_sc;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] program_sc_addr;
integer k;
begin
program_sc_addr = {ADDR_BITS{1'b0}};
program_sc_addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS]= addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS];
program_sc_addr[CADDR_BITS]=addr[CADDR_BITS]; //keep Ra0 for odd even selection
if (program_sc_addr[ADDR_BITS-1] === 1'b0)
begin
for(k=0;k<SECTOR_ROWS;k=k+2)
begin
program_wl(program_sc_addr);
program_sc_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]=program_sc_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]+2;
end
end
else if (program_sc_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Program Sector in special rows is not allowed. Executing Program WL in %m @ %d",$time);
end
//call program wl when ax is i
program_wl(addr);
end
end
endtask
task program_sc_all;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] program_sc_all_addr;
integer k;
begin
program_sc_all_addr = {ADDR_BITS{1'b0}};
program_sc_all_addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS]=addr[ADDR_BITS-1:CADDR_BITS+RADDR_BITS];
if (program_sc_all_addr[ADDR_BITS-1] === 1'b0)
begin
for(k=0;k<SECTOR_ROWS;k=k+1)
begin
program_wl(program_sc_all_addr);
program_sc_all_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]=program_sc_all_addr[RADDR_BITS+CADDR_BITS-1:CADDR_BITS]+1;
end
end
else if (program_sc_all_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Program Sector All in special rows is not allowed. Executing Program WL in %m @ %d",$time);
end
//call program wl when ax is i
program_wl(addr);
end
end
endtask
task program_bk;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] program_bk_addr;
integer k;
begin
program_bk_addr = {ADDR_BITS{1'b0}};
program_bk_addr[ADDR_BITS-1]=addr[ADDR_BITS-1];
program_bk_addr[CADDR_BITS]=addr[CADDR_BITS];//keep Ra0 for odd even program
if (program_bk_addr[ADDR_BITS-1] === 1'b0)
begin
program_sc(program_bk_addr); // one sector, just pass address
/*
for(k=0;k<SECTORS;k=k+1)
begin
// if ((k != 3) && (k != 7)) // skip the 4 sector in each plane (48k instead of 64k)
begin
program_bk_addr[BADDR_BITS+RADDR_BITS+CADDR_BITS-1:RADDR_BITS+CADDR_BITS] = k;
program_sc(program_bk_addr);
end
end
*/
end
else if (program_bk_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Program Bulk in special rows is not allowed. Executing Program WL in %m @ %d",$time);
end
//call program word-line when ax is 1
program_wl(addr);
end
end
endtask
task program_bk_all;
//parameter ADDR_BITS = 16;
input [ADDR_BITS-1:0] addr;
reg [ADDR_BITS-1:0] program_bk_all_addr;
integer k;
begin
program_bk_all_addr = {ADDR_BITS{1'b0}};
program_bk_all_addr[ADDR_BITS-1]=addr[ADDR_BITS-1];
if (program_bk_all_addr[ADDR_BITS-1] === 1'b0)
begin
program_sc_all(program_bk_all_addr); // one sector; just pass the address
/*
for(k=0;k<SECTORS;k=k+1)
begin
// if ((k != 3) && (k != 7)) // skip the 4 sector in each plane (48k instead of 64k)
begin
program_bk_all_addr[BADDR_BITS+RADDR_BITS+CADDR_BITS-1:RADDR_BITS+CADDR_BITS] = k;
program_sc_all(program_bk_all_addr);
end
end
*/
end
else if (program_bk_all_addr[ADDR_BITS-1] === 1'b1)
begin
if ((print_enable))
begin
$display("===WARNING=== s8fmlt_32k_sys: Program Bulk All in special rows is not allowed. Executing Program WL in %m @ %d",$time);
end
//call program word-line when ax is 1
program_wl(addr);
end
end
endtask
// ----- corrupt memory engine----
event corrupt_mem;
reg [ADDR_BITS-1:0] corrupt_address;
always @(corrupt_mem)
begin
memory[corrupt_address] = ~memory[corrupt_address];
end
assign xy_out_iso= (p_up===1'b0)?1'bx:
(^tm_xydec===1'bx)?1'bx:
(tm_xydec===1'b0)?1'b0:
(iref!==1'b1)?1'bx:
((~tm_disrow)&&(~tm_encol));
assign xy_out =(iso===1'b1)?(gnd_good?1'b0:1'bx):
(iso===1'b0)?xy_out_iso:1'bx;
//---
initial
begin
tpclk00 = 0;
tpclk11 = 0;
tpclk10 = 0.0;
prev_seq_sample = 0.0;
pclk_toggle = 0;
pclk_period_good = 1'b0;
pump_timing_error = 1'b0;
end
/*
always @(posedge pclk or negedge p_up_analog)
begin
if (p_up_analog === 1'b1)
begin
tpclk00 = tpclk11;
tpclk11 = $realtime;
if(tpclk00 > 0) // tpclk 0 means firt ed
begin
if(((tpclk11 - tpclk00) <= TPCLK_MAX) &&
((tpclk11 - tpclk00) >= TPCLK_MIN))
begin
pclk_toggle = 1;
end
else
begin
pclk_toggle = 0;
end
end
end
else // power is bad - reset all the time variables and switch pclk_toggle off
begin
pclk_toggle = 0;
tpclk00 = 0;
tpclk11 = 0;
end
end
*/
always @(negedge pclk or negedge p_up_analog)
begin
if (p_up_analog === 1'b1)
begin
if (pclk === 1'b0)
begin
tpclk10 = $realtime;
if(((tpclk10 - tpclk11) >= 0.4*(tpclk11 - tpclk00))&&
((tpclk10 - tpclk11) <= 0.6*(tpclk11 - tpclk00)))
begin
pclk_pulse = 1;
end
else
begin
pclk_pulse = 0;
end
end
else
begin
pclk_pulse = 0;
tpclk10 = 0.0;
end
end
else
begin
pclk_pulse = 0;
tpclk10 = 0.0;
end
end
always @(posedge pclk or negedge p_up_analog)
begin
if (p_up_analog === 1'b1)
begin
if(pclk === 1'b1)
begin
tpclk00 = tpclk11;
tpclk11 = $realtime;
if ((tpclk00 > 0) && ((tpclk11 - tpclk00) < TPCLK_MIN))
begin
pclk_period_good = 1'b0;
end
else
begin
pclk_period_good = 1'b1;
end
end
else
begin
pclk_period_good = 1'b0;
end
end
else
begin
pclk_period_good = 1'b0;
tpclk00 = 0;
tpclk11 = 0;
end
disable pclk_toggle_gen;
#0;
-> pclk_event;
end
always @(pclk_event)
begin:pclk_toggle_gen
if (pclk_period_good === 1'b1)
begin
pclk_toggle = 1'b1;
#TPCLK_MAX;
end
pclk_toggle = 1'b0;
end
`endif //ATPG_SIM
//---
assign tchk_and_not_scan_mode = power_good && ~scan_mode;
assign not_scan_en = ~scan_en;
assign not_pe = !pe;
assign pe_and_not_scan_mode = pe && ~scan_mode;
assign not_scan_mode = ~scan_mode;
`ifdef functional
assign dclk = clk;
assign dpe = pe;
assign dscan_in1 = scan_in1;
assign dscan_in2 = scan_in2;
assign dpa = pa;
assign dpw = pw;
assign ddi = di;
assign dra = ra;
assign dseq = seq;
//assign dba = ba;
assign dca = ca;
assign dmode = mode;
assign daxa = axa;
assign dpdac = pdac;
assign dndac = ndac;
assign dpnb = pnb;
assign dtm = tm;
assign dreset = reset;
assign dturbo_b = turbo_b;
assign dsleep = sleep;
`else
specify
specparam S8FMLT_32K_SYS_TCY = 51; //AC 3.2
specparam S8FMLT_32K_SYS_TCY_S = 18; //AC 3.2
specparam S8FMLT_32K_SYS_TAWH = 6; //AC 3.5
specparam S8FMLT_32K_SYS_TAWL = 6; //AC 3.6
specparam S8FMLT_32K_SYS_TAS = 3.5;//AC 3.3
specparam S8FMLT_32K_SYS_TAH = 0; //AC 3.4
specparam S8FMLT_32K_SYS_TPE_PRG_MIN = 1000;
specparam S8FMLT_32K_SYS_TSW = 20; //AC 3.23
specparam S8FMLT_32K_SYS_TS2P = 10000; //AC 3.10
specparam S8FMLT_32K_SYS_TPS3 = 50000; //AC 3.15
specparam S8FMLT_32K_SYS_TRW1 = 20; //AC 3.21
specparam S8FMLT_32K_SYS_TRW2 = 7000; //AC 3.22
specparam S8FMLT_32K_SYS_CLK_REC_PE = S8FMLT_32K_SYS_TPE_PRG_MIN+S8FMLT_32K_SYS_TPS3;
specparam S8FMLT_32K_SYS_TAA = 48;// 50 ns data out access time AC 3.1
specparam S8FMLT_32K_SYS_PUMPS = 3.5;// setup time; ndac/pdac - posedge pe //AC 3.3
specparam S8FMLT_32K_SYS_PUMPH = 0;// hold time; ndac/pdac - posedge pe //AC 3.4
specparam S8FMLT_32K_SYS_TAA_S = 10;//AC 3.28
specparam S8FMLT_32K_SYS_TRCS = 20;//AC 3.20
specparam S8FMLT_32K_SYS_TIDS = 10;//AC 3.27
specparam S8FMLT_32K_SYS_TACTIVE = 5000;//AC3.26
specparam S8FMLT_32K_SYS_TACTIVE1 = 80;//AC3.TBD
specparam S8FMLT_32K_SYS_TTURBO = 5000; //AC3.25
specparam S8FMLT_32K_SYS_TISO = 200; //AC2.TBD
//------------------------------------------------------------
// The specify block is imported form the S8FMLT_32K_SYS_top
// All parameters are defined in the header file (s8fm_h_32.v)
//------------------------------------------------------------
$period(posedge clk &&& not_scan_mode,S8FMLT_32K_SYS_TCY,notifier_clk );
$period(posedge clk &&& scan_mode,S8FMLT_32K_SYS_TCY_S,notifier_clk );
$width (posedge clk &&& power_good,S8FMLT_32K_SYS_TAWH,,notifier_clk );
$width (negedge clk &&& power_good,S8FMLT_32K_SYS_TAWL,,notifier_clk );
//$recovery(negedge pe,posedge clk &&& tchk_and_not_scan_mode,S8FMLT_32K_SYS_TPS3) ;
$recrem(negedge pe,posedge clk ,S8FMLT_32K_SYS_TPS3,0,notifier_pe,tchk_and_not_scan_mode,power_good,dpe,dclk) ;
//$recovery(posedge pe,posedge clk &&& tchk_and_not_scan_mode,S8FMLT_32K_SYS_CLK_REC_PE) ;
//$recovery(negedge reset,posedge clk &&& tchk,0) ;
$recrem(negedge reset &&& power_good,posedge clk ,S8FMLT_32K_SYS_TRCS,0,notifier_rst,,,dreset,dclk) ;
$recrem(negedge iso &&& power_good,posedge clk ,S8FMLT_32K_SYS_TACTIVE1,0,notifier_iso,,,diso,dclk) ;
$recrem(negedge pd2 &&& power_good,posedge clk ,S8FMLT_32K_SYS_TACTIVE,0,notifier_pd2,,,dpd2,dclk) ;
//$recovery(posedge turbo_b,posedge clk &&& tchk,0);
$recrem(posedge turbo_b &&& power_good,posedge clk,S8FMLT_32K_SYS_TIDS,0,notifier_tbb,,,dturbo_b,dclk);
$setuphold (posedge clk ,posedge pe,0,S8FMLT_32K_SYS_TS2P ,notifier_pe,tchk_and_not_scan_mode,power_good, dclk, dpe);
$width( posedge pe &&& tchk_and_not_scan_mode,S8FMLT_32K_SYS_TPE_PRG_MIN,,notifier_pe );
$width( posedge sleep,S8FMLT_32K_SYS_TSW );
//$recovery(negedge sleep,posedge turbo_b,0);
$recrem(negedge sleep,posedge turbo_b,S8FMLT_32K_SYS_TTURBO,0,,,,dsleep,dturbo_b); // this is sleep to clk and it is already used in iref timing
$width(posedge reset &&& not_pe,S8FMLT_32K_SYS_TRW1,,notifier_rstw);
$width(posedge reset &&& pe_and_not_scan_mode ,S8FMLT_32K_SYS_TRW2,,notifier_rstw);
$width(posedge pclk,S8FMLT_32K_SYS_TAWH);
$width(negedge pclk,S8FMLT_32K_SYS_TAWL);
//$setup(posedge scan_in &&& tchk, posedge clk &&& scan_mode, S8FMLT_32K_SYS_TAS,notifier_scan);
//$setup(negedge scan_in &&& tchk, posedge clk &&& scan_mode, S8FMLT_32K_SYS_TAS,notifier_scan);
$setuphold(posedge clk, posedge scan_in1, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_scan1,scan_mode,power_good,dclk,dscan_in1);
$setuphold(posedge clk, negedge scan_in1, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_scan1,scan_mode,power_good,dclk,dscan_in1);
$setuphold(posedge clk, posedge scan_in2, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_scan2,scan_mode,power_good,dclk,dscan_in2);
$setuphold(posedge clk, negedge scan_in2, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_scan2,scan_mode,power_good,dclk,dscan_in2);
if (not_scan_mode)(posedge clk => (xy_out : clk ) ) = (0:0:0,0:0:0);
// Might require to go back to (0:0:0,0:0:0) format after sdf verification
if(not_scan_mode)(posedge clk => (dout[0] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[0] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[1] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[1] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[2] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[2] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[3] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[3] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[4] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[4] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[5] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[5] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[6] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[6] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[7] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[7] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[8] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[8] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[9] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[9] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[10] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[10] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[11] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[11] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[12] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[12] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[13] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[13] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[14] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[14] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[15] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[15] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[16] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[16] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[17] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[17] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[18] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[18] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[19] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[19] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[20] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[20] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[21] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[21] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[22] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[22] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[23] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[23] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[24] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[24] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[25] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[25] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[26] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[26] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[27] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[27] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[28] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[28] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[29] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[29] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[30] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[30] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[31] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[31] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[32] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[32] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[33] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[33] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[34] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[34] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[35] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[35] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[36] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[36] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[37] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[37] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[38] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[38] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[39] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[39] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[40] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[40] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[41] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[41] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[42] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[42] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[43] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[43] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[44] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[44] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[45] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[45] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[46] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[46] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[47] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[47] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[48] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[48] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[49] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[49] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[50] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[50] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[51] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[51] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[52] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[52] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[53] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[53] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[54] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[54] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[55] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[55] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[56] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[56] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[57] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[57] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[58] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[58] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[59] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[59] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[60] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[60] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[61] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[61] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[62] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[62] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
if(not_scan_mode)(posedge clk => (dout[63] : clk ) ) = S8FMLT_32K_SYS_TAA;
if(scan_mode)(posedge clk => (dout[63] : clk ) ) = S8FMLT_32K_SYS_TAA_S;
(posedge clk => (scan_out1 : clk ) ) = S8FMLT_32K_SYS_TAA_S;
(posedge clk => (scan_out2 : clk ) ) = S8FMLT_32K_SYS_TAA_S;
(iso => (dout[0] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[1] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[2] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[3] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[4] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[5] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[6] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[7] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[8] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[9] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[10] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[11] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[12] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[13] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[14] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[15] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[16] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[17] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[18] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[19] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[20] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[21] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[22] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[23] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[24] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[25] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[26] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[27] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[28] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[29] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[30] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[31] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[32] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[33] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[34] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[35] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[36] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[37] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[38] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[39] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[40] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[41] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[42] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[43] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[44] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[45] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[46] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[47] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[48] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[49] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[50] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[51] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[52] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[53] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[54] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[55] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[56] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[57] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[58] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[59] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[60] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[61] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[62] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (dout[63] : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (scan_out1 : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (scan_out2 : iso ) ) = S8FMLT_32K_SYS_TISO;
(iso => (xy_out : iso ) ) = S8FMLT_32K_SYS_TISO;
$setuphold(posedge clk, posedge pa[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[6]);
$setuphold(posedge clk, negedge pa[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[6]);
$setuphold(posedge clk, posedge pa[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[5]);
$setuphold(posedge clk, negedge pa[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[5]);
$setuphold(posedge clk, posedge pa[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[4]);
$setuphold(posedge clk, negedge pa[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[4]);
$setuphold(posedge clk, posedge pa[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[3]);
$setuphold(posedge clk, negedge pa[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[3]);
$setuphold(posedge clk, posedge pa[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[2]);
$setuphold(posedge clk, negedge pa[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[2]);
$setuphold(posedge clk, posedge pa[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[1]);
$setuphold(posedge clk, negedge pa[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[1]);
$setuphold(posedge clk, posedge pa[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[0]);
$setuphold(posedge clk, negedge pa[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pa ,not_scan_en,power_good, dclk, dpa[0]);
$setuphold(posedge clk, posedge pw, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pw ,not_scan_en,power_good, dclk, dpw);
$setuphold(posedge clk, negedge pw, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pw ,not_scan_en,power_good, dclk, dpw);
$setuphold(posedge clk,posedge di[7], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[7] );
$setuphold(posedge clk,negedge di[7], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[7] );
$setuphold(posedge clk,posedge di[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[6] );
$setuphold(posedge clk,negedge di[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[6] );
$setuphold(posedge clk,posedge di[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[5] );
$setuphold(posedge clk,negedge di[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[5] );
$setuphold(posedge clk,posedge di[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[4] );
$setuphold(posedge clk,negedge di[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[4] );
$setuphold(posedge clk,posedge di[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[3] );
$setuphold(posedge clk,negedge di[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[3] );
$setuphold(posedge clk,posedge di[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[2] );
$setuphold(posedge clk,negedge di[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[2] );
$setuphold(posedge clk,posedge di[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[1] );
$setuphold(posedge clk,negedge di[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[1] );
$setuphold(posedge clk,posedge di[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[0] );
$setuphold(posedge clk,negedge di[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_di ,not_scan_en,power_good, dclk, ddi[0] );
$setuphold(posedge clk,posedge ra[7], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[7] );
$setuphold(posedge clk,negedge ra[7], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[7] );
$setuphold(posedge clk,posedge ra[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[6] );
$setuphold(posedge clk,negedge ra[6], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[6] );
$setuphold(posedge clk,posedge ra[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[5] );
$setuphold(posedge clk,negedge ra[5], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[5] );
$setuphold(posedge clk,posedge ra[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[4] );
$setuphold(posedge clk,negedge ra[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[4] );
$setuphold(posedge clk,posedge ra[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[3] );
$setuphold(posedge clk,negedge ra[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[3] );
$setuphold(posedge clk,posedge ra[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[2] );
$setuphold(posedge clk,negedge ra[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[2] );
$setuphold(posedge clk,posedge ra[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[1] );
$setuphold(posedge clk,negedge ra[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[1] );
$setuphold(posedge clk,posedge ra[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[0] );
$setuphold(posedge clk,negedge ra[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dra[0] );
$setuphold(posedge clk,posedge seq[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_seq ,not_scan_en,power_good, dclk, dseq[1] );
$setuphold(posedge clk,negedge seq[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_seq ,not_scan_en,power_good, dclk, dseq[1] );
$setuphold(posedge clk,posedge seq[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_seq ,not_scan_en,power_good, dclk, dseq[0] );
$setuphold(posedge clk,negedge seq[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_seq ,not_scan_en,power_good, dclk, dseq[0] );
$setuphold(posedge clk,posedge ca[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[3] );
$setuphold(posedge clk,negedge ca[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[3] );
$setuphold(posedge clk,posedge ca[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[2] );
$setuphold(posedge clk,negedge ca[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[2] );
$setuphold(posedge clk,posedge ca[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[1] );
$setuphold(posedge clk,negedge ca[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[1] );
$setuphold(posedge clk,posedge ca[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[0] );
$setuphold(posedge clk,negedge ca[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, dca[0] );
$setuphold(posedge clk,posedge mode[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[3] );
$setuphold(posedge clk,negedge mode[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[3] );
$setuphold(posedge clk,posedge mode[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[2] );
$setuphold(posedge clk,negedge mode[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[2] );
$setuphold(posedge clk,posedge mode[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[1] );
$setuphold(posedge clk,negedge mode[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[1] );
$setuphold(posedge clk,posedge mode[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[0] );
$setuphold(posedge clk,negedge mode[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_mode ,not_scan_en,power_good, dclk, dmode[0] );
$setuphold(posedge clk,posedge axa, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, daxa );
$setuphold(posedge clk,negedge axa, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_addr ,not_scan_en,power_good, dclk, daxa );
$setuphold(posedge clk,posedge tm[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[4] );
$setuphold(posedge clk,negedge tm[4], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[4] );
$setuphold(posedge clk,posedge tm[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[3] );
$setuphold(posedge clk,negedge tm[3], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[3] );
$setuphold(posedge clk,posedge tm[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[2] );
$setuphold(posedge clk,negedge tm[2], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[2] );
$setuphold(posedge clk,posedge tm[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[1] );
$setuphold(posedge clk,negedge tm[1], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[1] );
$setuphold(posedge clk,posedge tm[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[0] );
$setuphold(posedge clk,negedge tm[0], S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_tm ,not_scan_en,power_good, dclk, dtm[0] );
$setuphold(posedge clk,posedge pnb, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pnb ,not_scan_en,power_good, dclk, dpnb );
$setuphold(posedge clk,negedge pnb, S8FMLT_32K_SYS_TAS, S8FMLT_32K_SYS_TAH, notifier_pnb ,not_scan_en,power_good, dclk, dpnb );
$setuphold(posedge pe,posedge ndac[3], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[3] );
$setuphold(posedge pe,negedge ndac[3], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[3] );
$setuphold(posedge pe,posedge ndac[2], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[2] );
$setuphold(posedge pe,negedge ndac[2], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[2] );
$setuphold(posedge pe,posedge ndac[1], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[1] );
$setuphold(posedge pe,negedge ndac[1], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[1] );
$setuphold(posedge pe,posedge ndac[0], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[0] );
$setuphold(posedge pe,negedge ndac[0], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dndac[0] );
$setuphold(posedge pe,posedge pdac[3], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[3] );
$setuphold(posedge pe,negedge pdac[3], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[3] );
$setuphold(posedge pe,posedge pdac[2], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[2] );
$setuphold(posedge pe,negedge pdac[2], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[2] );
$setuphold(posedge pe,posedge pdac[1], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[1] );
$setuphold(posedge pe,negedge pdac[1], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[1] );
$setuphold(posedge pe,posedge pdac[0], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[0] );
$setuphold(posedge pe,negedge pdac[0], S8FMLT_32K_SYS_PUMPS, S8FMLT_32K_SYS_PUMPH, notifier_pump ,not_scan_mode,power_good, dpe, dpdac[0] );
endspecify
`endif
`ifdef ATPG_SIM
`else
always @(posedge dclk)
begin
#(S8FMLT_32K_TAW + 2);
reset_notifier_errors = 1'b1;
#1;
reset_notifier_errors = 1'b0;
end
always @(notifier_rstw)
begin //generate an internal reset pulse that will reset to x not 0
reset_x = 1'b1;
#1;
reset_x = 1'b0;
end
always @(notifier_rst or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
rst_timing_error = 1'b0;
end
else
begin
rst_timing_error = 1'b1;
end
end
always @(notifier_pd2 or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
pd2_timing_error = 1'b0;
end
else
begin
pd2_timing_error = 1'b1;
end
end
always @(notifier_tbb or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
tbb_timing_error = 1'b0;
end
else
begin
tbb_timing_error = 1'b1;
end
end
always @(notifier_iso or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
iso_timing_error = 1'b0;
end
else
begin
iso_timing_error = 1'b1;
end
end
always @(notifier_addr or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
addr_timing_error = 1'b0;
end
else
begin
addr_timing_error = 1'b1;
end
end
always @(notifier_seq or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
seq_timing_error = 1'b0;
end
else
begin
seq_timing_error = 1'b1;
end
end
always @(notifier_mode or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
mode_timing_error = 1'b0;
end
else
begin
mode_timing_error = 1'b1;
end
end
always @(notifier_clk or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
clk_timing_error = 1'b0;
end
else
begin
clk_timing_error = 1'b1;
end
end
always @(notifier_di or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
di_timing_error = 1'b0;
end
else
begin
di_timing_error = 1'b1;
end
end
always @(notifier_pw or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
pw_timing_error = 1'b0;
end
else
begin
pw_timing_error = 1'b1;
end
end
always @(notifier_pnb or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
pnb_timing_error = 1'b0;
end
else
begin
pnb_timing_error = 1'b1;
end
end
always @(notifier_pa or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
pa_timing_error = 1'b0;
end
else
begin
pa_timing_error = 1'b1;
end
end
always @(notifier_tm or posedge reset_notifier_errors or posedge dreset)
begin
if ((reset_notifier_errors===1'b1)||(dreset === 1'b1))
begin
tm_timing_error = 1'b0;
end
else
begin
tm_timing_error = 1'b1;
end
end
always @(notifier_pe or posedge dreset)
begin
if (dreset === 1'b1)
begin
pe_timing_error = 1'b0;
end
else
begin
pe_timing_error = 1'b1;
end
end
always @(notifier_pump or posedge reset_pump_timing_error or posedge dreset)
begin
if ((reset_pump_timing_error)||(dreset === 1'b1))
begin
pump_timing_error = 1'b0;
end
else
begin
pump_timing_error = 1'b1;
end
end
`endif // ATPG_SIM
`ifdef ATPG_SIM
always @(notifier_addr)
begin
fm32k_top.fm32k_nsw.predec.rpre.raddlat_10_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_9_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_8_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_7_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_6_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_5_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_4_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_3_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_2_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_1_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_0_.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat5.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat4.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat3.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat2.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat1.nfr <= notifier_addr;
fm32k_top.fm32k_nsw.predec.cpren.cadlat0.nfr <= notifier_addr;
end
always @(notifier_seq)
begin
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_seq_reg_1_.nfr <= notifier_seq;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_seq_reg_0_.nfr <= notifier_seq;
end
always @(notifier_mode)
begin
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_3_.nfr <= notifier_mode;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_2_.nfr <= notifier_mode;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_1_.nfr <= notifier_mode;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_0_.nfr <= notifier_mode;
end
always @(notifier_scan1)
begin
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_0_.nfr <= notifier_scan1;
end
always @(notifier_scan2)
begin
fm32k_top.fm32k_nsw.spine16x64.sa64.sa8_fm_0_.saout_fm_0_.dout_scan.scan_ff.nfr <= notifier_scan2;
end
always @(notifier_di)
begin
fm32k_top.fm32k_nsw.dinpg.dilat_7_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_6_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_5_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_4_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_3_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_2_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_1_.nfr <= notifier_di;
fm32k_top.fm32k_nsw.dinpg.dilat_0_.nfr <= notifier_di;
end
always @(notifier_pa)
begin
fm32k_top.fm32k_nsw.dinpg.palat_6_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_5_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_4_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_3_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_2_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_1_.nfr <= notifier_pa;
fm32k_top.fm32k_nsw.dinpg.palat_0_.nfr <= notifier_pa;
end
always @(notifier_pw)
begin
fm32k_top.fm32k_nsw.dinpg.pwlat.nfr <= notifier_pw;
end
always @(notifier_pnb)
begin
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.pnblat.nfr <= notifier_pnb;
end
always @(notifier_tm)
begin
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_4_.nfr <= notifier_tm;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_3_.nfr <= notifier_tm;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_2_.nfr <= notifier_tm;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_1_.nfr <= notifier_tm;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_0_.nfr <= notifier_tm;
end
//clk
always @(notifier_clk)
begin
fm32k_top.fm32k_nsw.predec.rpre.raddlat_10_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_9_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_8_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_7_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_6_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_5_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_4_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_3_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_2_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_1_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.rpre.raddlat_0_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat5.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat4.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat3.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat2.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat1.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.predec.cpren.cadlat0.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_seq_reg_1_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_seq_reg_0_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_3_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_2_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_1_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.mpcont.mpcon_top.mpcon.fi_mode_reg_0_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_7_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_6_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_5_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_4_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_3_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_2_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_1_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.dilat_0_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_6_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_5_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_4_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_3_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_2_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_1_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.palat_0_.nfr <= notifier_clk;
fm32k_top.fm32k_nsw.dinpg.pwlat.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.pnblat.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_4_.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_3_.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_2_.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_1_.nfr <= notifier_clk;
analog_top.tmcont.tmcont_nsw.tmcont_logic.tmcont_in.tmlat_0_.nfr <= notifier_clk;
end
`endif //ATPG_SIM notifier pass to scan chain
endmodule