| simLibName = "oscDesign" |
| simCellName = "CELL_NAME" |
| simViewName = "schematic" |
| simSimulator = "auCdl" |
| simNotIncremental = nil |
| simReNetlistAll = nil |
| simViewList = '("auCdl" "schematic") |
| simStopList = '("auCdl") |
| simNetlistHier = t |
| hnlNetlistFileName = "CELL_NAME.cdl" |
| resistorModel = "" |
| shortRES = 2000.0 |
| preserveRES = 'nil |
| checkRESVAL = 'nil |
| checkRESSIZE = 'nil |
| preserveCAP = 'nil |
| checkCAPVAL = 'nil |
| checkCAPAREA = 'nil |
| preserveDIO = 'nil |
| checkDIOAREA = 'nil |
| checkDIOPERI = 'nil |
| checkCAPPERI = 'nil |
| checkScale = "meter" |
| checkLDD = 'nil |
| pinMAP = 'nil |
| shrinkFACTOR = 0.0 |
| globalPowerSig = "" |
| globalGndSig = "" |
| displayPININFO = 't |
| preserveALL = 'nil |
| setEQUIV = "" |
| incFILE = "" |