blob: 246efb2140c0fabd1e0fda2f1c72e600e42ba5ed [file] [log] [blame]
// Automatically modified by replacePGwithIfDef.pl
// iptguser Thu Aug 18 13:10:20 EDT 2011
// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser Mon Aug 8 14:40:04 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults
`celldefine
`timescale 1ns / 1ps
module scs8lp_o21bai_m (
output Y,
input A1,
input A2,
input B1N
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
wire b;
not (b,B1N);
or ( csi_opt_287 , A2 , A1 ) ;
nand ( UDP_IN_Y , b , csi_opt_287 ) ;
`ifdef SC_USE_PG_PIN
scs8lpa_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
buf (Y, UDP_OUT_Y) ;
`else
buf ( Y , UDP_IN_Y ) ;
`endif
// modification by BNB, based on SPR13943. need to have
`ifdef functional
`else
reg csi_notifier;
specify
(A1 -=> Y) = (0:0:0,0:0:0);
(A2 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0);
if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0);
if ((A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0);
endspecify
`endif
endmodule
`endcelldefine