scs8lp/V0.0.1/verilog/scs8lp_dlclkp_2.v

// Automatically modified by replacePGwithIfDef.pl
// iptguser	Thu Aug 18 13:10:16 EDT 2011

// Automatically edited by removePhraseFromMultipleFiles.pl
// iptguser	Mon Aug  8 14:40:00 EDT 2011
// \`suppress_faults;^\n
// \`ifdef TETRAMAX;^\n
// \`ifdef functional;\`else
// \`delay_mode_path;^\n
// \`disable_portfaults;\`nosuppress_faults

`celldefine
`timescale 1ns / 1ps
module scs8lp_dlclkp_2  (
output GCLK,

input GATE,
input CLK

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire m0;
  wire clkn;
  wire CLK_delayed;
  wire GATE_delayed;

`ifdef functional
  not (clkn,CLK);
`ifdef SC_USE_PG_PIN
 scs8lpa_U_DL_P_NO_pg #0.001 ( m0 , GATE , clkn ,  , vpwr , vgnd ) ;
`else
 scs8lpa_U_DL_P #0.001 ( m0 , GATE , clkn ) ;
`endif
  and (GCLK, m0, CLK);

`else
  reg notifier;
  not (clkn,CLK_delayed);
scs8lpa_U_DL_P_NO_pg  ( m0 , GATE_delayed , clkn , notifier , vpwr , vgnd ) ;
  and (GCLK, m0, CLK_delayed);

  specify
    (CLK +=> GCLK) = (0:0:0,0:0:0);                         // delays are tris,tfall
    $width (posedge CLK , 0:0:0, 0, notifier);
    $width (negedge CLK , 0:0:0, 0, notifier);
    $setuphold ( posedge CLK , posedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ;
    $setuphold ( posedge CLK , negedge GATE , 0:0:0, 0:0:0, notifier , , , CLK_delayed , GATE_delayed ) ;
  endspecify
`endif


endmodule
`endcelldefine