| 5-17-2019 | |
| The V0.0.1 version of the OA library differs from the V0.0.0 version in | |
| only minor respects: the supply pins vpwr, vgnd, vnb, vpb no longer have | |
| the property nlAction=ignore on the scs8hvl cells, and they now appear in | |
| the port order list for the symbol. | |
| This caused verilog in to not map the digital gates because the ports are | |
| different. Now verilog in should be able to map the gates. |