scs8hs/V0.0.1/verilog/scs8hs_xor3_1.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_xor3_1 ( X , A , B , C , vpwr, vgnd );
output  X ;
input  A , B , C , vpwr, vgnd ;

`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!B&!C)) (A +=> X) = (0:0:0,0:0:0);
    if ((!B&C)) (A -=> X) = (0:0:0,0:0:0);
    if ((B&!C)) (A -=> X) = (0:0:0,0:0:0);
    if ((B&C)) (A +=> X) = (0:0:0,0:0:0);
    if ((!A&!C)) (B +=> X) = (0:0:0,0:0:0);
    if ((!A&C)) (B -=> X) = (0:0:0,0:0:0);
    if ((A&!C)) (B -=> X) = (0:0:0,0:0:0);
    if ((A&C)) (B +=> X) = (0:0:0,0:0:0);
    if ((!A&!B)) (C +=> X) = (0:0:0,0:0:0);
    if ((!A&B)) (C -=> X) = (0:0:0,0:0:0);
    if ((A&!B)) (C -=> X) = (0:0:0,0:0:0);
    if ((A&B)) (C +=> X) = (0:0:0,0:0:0);
	endspecify
`endif

  xor ( UDP_IN_X , A , B , C ) ;
  U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults