scs8hs/V0.0.1/verilog/scs8hs_sdfstp_2.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 


module scs8hs_sdfstp_2 ( CLK , D , Q , SCD , SCE , SETB , vpwr , vgnd ) ; 
input vpwr , vgnd ; 

output  Q ; 
input   CLK , D , SCD , SCE , SETB ; 
wire  buf_Q , set , mux_out ; 

`ifdef functional
  not ( set , SETB ) ; 
  U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
U_DF_P_S_pg #0.001 ( buf_Q , mux_out , CLK , set , vpwr , vgnd ) ; 
`else
  reg notifier ; 
  wire D_delayed , SCD_delayed , SCE_delayed , SETB_delayed , CLK_delayed ; 
  not ( set , SETB_delayed ) ; 
  U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE , COND0 , COND1 , COND2 , COND3 , COND4 ; 
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    ( negedge SETB => ( Q -: SETB ) ) = 0:0:0 ;  // delay is tris
    ( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults