scs8hs/V0.0.1/verilog/scs8hs_o41a_2.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_o41a_2 ( X ,  A1 , A2 , A3 , A4 , B1 , vpwr , vgnd );
input vpwr, vgnd;
output  X ;
input  A1 , A2 , A3 , A4 , B1 ;

wire	X , A1 , A2 , A3 ;
wire	A4 , B1 , csi_opt_297 ;

`ifdef functional
`else
reg csi_notifier;

	specify
    (A1 +=> X) = (0:0:0,0:0:0);
    (A2 +=> X) = (0:0:0,0:0:0);
    (A3 +=> X) = (0:0:0,0:0:0);
    (A4 +=> X) = (0:0:0,0:0:0);
    if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
    if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
	endspecify
`endif

  or ( csi_opt_297 , A4 , A3 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_297 , B1 ) ;
  U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults