scs8hs/V0.0.1/verilog/scs8hs_mux2i_2.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_mux2i_2 ( Y ,  A0 , A1 , S , vpwr , vgnd );
input vpwr, vgnd;
output  Y ;
input  A0 , A1 , S ;

wire	Y , A0 , A1 , S ;

`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0);
    if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0);
    if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0);
    if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0);
    if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0);
    if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0);
	endspecify
`endif
   
  // aug27,2003 - bnb changed to udp model for muxs
   
  U_MUX_2_1_INV (UDP_IN_Y, A0, A1, S);
  U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
   
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults