scs8hs/V0.0.1/verilog/scs8hs_ha_4.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_ha_4 ( COUT , SUM ,  A , B , vpwr , vgnd );
input vpwr, vgnd;
output  COUT , SUM ;
input  A , B ;

wire	COUT , SUM , A , B ;

`ifdef functional
`else
reg csi_notifier;

	specify
    (A +=> COUT) = (0:0:0,0:0:0);
    (B +=> COUT) = (0:0:0,0:0:0);
    if ((!B)) (A +=> SUM) = (0:0:0,0:0:0);
    if ((B)) (A -=> SUM) = (0:0:0,0:0:0);
    if ((!A)) (B +=> SUM) = (0:0:0,0:0:0);
    if ((A)) (B -=> SUM) = (0:0:0,0:0:0);
	endspecify
`endif

  and  ( UDP_IN_COUT , A , B ) ;
  U_VPWR_VGND (UDP_OUT_COUT, UDP_IN_COUT, vpwr, vgnd) ;
  buf  (COUT, UDP_OUT_COUT) ;
  xor  ( UDP_IN_SUM , B , A ) ;
  U_VPWR_VGND (UDP_OUT_SUM, UDP_IN_SUM, vpwr, vgnd) ;
  buf  (SUM, UDP_OUT_SUM) ;
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults