scs8hs/V0.0.1/verilog/scs8hs_fah_4.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_fah_4 ( COUT , SUM ,  A , B , CI, vpwr , vgnd );
output  COUT , SUM ;
input  A , B , CI, vpwr , vgnd ;

`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!B&CI)) (A +=> COUT) = (0:0:0,0:0:0);
    if ((B&!CI)) (A +=> COUT) = (0:0:0,0:0:0);
    if ((!A&CI)) (B +=> COUT) = (0:0:0,0:0:0);
    if ((A&!CI)) (B +=> COUT) = (0:0:0,0:0:0);
    if ((!A&B)) (CI +=> COUT) = (0:0:0,0:0:0);
    if ((A&!B)) (CI +=> COUT) = (0:0:0,0:0:0);
    if ((!B&!CI)) (A +=> SUM) = (0:0:0,0:0:0);
    if ((!B&CI)) (A -=> SUM) = (0:0:0,0:0:0);
    if ((B&!CI)) (A -=> SUM) = (0:0:0,0:0:0);
    if ((B&CI)) (A +=> SUM) = (0:0:0,0:0:0);
    if ((!A&!CI)) (B +=> SUM) = (0:0:0,0:0:0);
    if ((!A&CI)) (B -=> SUM) = (0:0:0,0:0:0);
    if ((A&!CI)) (B -=> SUM) = (0:0:0,0:0:0);
    if ((A&CI)) (B +=> SUM) = (0:0:0,0:0:0);
    if ((!A&!B)) (CI +=> SUM) = (0:0:0,0:0:0);
    if ((!A&B)) (CI -=> SUM) = (0:0:0,0:0:0);
    if ((A&!B)) (CI -=> SUM) = (0:0:0,0:0:0);
    if ((A&B)) (CI +=> SUM) = (0:0:0,0:0:0);
	endspecify
`endif

  xor (UDP_IN_SUM,A,B,CI);
  U_VPWR_VGND (UDP_OUT_SUM, UDP_IN_SUM, vpwr, vgnd) ;
  buf  (SUM, UDP_OUT_SUM) ;

  and (A$B,A,B),(A$CI,A,CI),(B$CI,B,CI);
  or (UDP_IN_COUT,A$B,A$CI,B$CI);
  U_VPWR_VGND (UDP_OUT_COUT, UDP_IN_COUT, vpwr, vgnd) ;
  buf  (COUT, UDP_OUT_COUT) ;

endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults