scs8hs/V0.0.1/verilog/scs8hs_ebufn_4.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 


module scs8hs_ebufn_4 (A,TEB,Z, vpwr , vgnd );
input vpwr, vgnd;
output  Z;
input   A,TEB;

  U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
bufif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

`ifdef functional
`else
	specify
		if (~TEB ) (A +=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
		(TEB => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
	endspecify
`endif

endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults