scs8hs/V0.0.1/verilog/scs8hs_a2bb2oi_2.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_a2bb2oi_2 ( Y ,  A1N , A2N , B1 , B2 , vpwr , vgnd );
input vpwr, vgnd;
output  Y ;
input  A1N , A2N , B1 , B2 ;

wire	Y , A1N , A2N , B1 ;
wire	B2 , csi_opt_273, csi_opt_274 ;

`ifdef functional
`else
reg csi_notifier;

	specify
    if ((!A2N&!B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0);
    if ((!A2N&!B1&B2)) (A1N +=> Y) = (0:0:0,0:0:0);
    if ((!A2N&B1&!B2)) (A1N +=> Y) = (0:0:0,0:0:0);
    if ((!A1N&!B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0);
    if ((!A1N&!B1&B2)) (A2N +=> Y) = (0:0:0,0:0:0);
    if ((!A1N&B1&!B2)) (A2N +=> Y) = (0:0:0,0:0:0);
    if ((!A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
    if ((A1N&!A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
    if ((A1N&A2N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
    if ((!A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
    if ((A1N&!A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
    if ((A1N&A2N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
	endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults