blob: 8759a7c59b1e97d818fb20b0b63718f28abec392 [file] [log] [blame]
`celldefine
`suppress_faults
`enable_portfaults
`ifdef TETRAMAX
`define functional
`endif
`ifdef functional
`timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
`delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
`delay_mode_unit
`endif
`else
`timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
`delay_mode_path
`endif
`endif
module scs8hs_a221oi_1 ( Y , A1 , A2 , B1 , B2 , C1 , vpwr , vgnd );
input vpwr, vgnd;
output Y ;
input A1 , A2 , B1 , B2 , C1 ;
wire Y , A1 , A2 , B1 ;
wire B2 , C1 , csi_opt_275, csi_opt_276 ;
`ifdef functional
`else
reg csi_notifier;
specify
if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
endspecify
`endif
and ( csi_opt_275 , B1 , B2 ) ;
and ( csi_opt_276 , A1 , A2 ) ;
nor ( UDP_IN_Y , csi_opt_275 , C1 , csi_opt_276 ) ;
U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
buf (Y, UDP_OUT_Y) ;
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults