scs8hs/V0.0.1/verilog/scs8hs_a21boi_4.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_a21boi_4 (Y,A1,A2,B1N, vpwr , vgnd );
input vpwr, vgnd;
output  Y;
input   A1,A2,B1N;
   wire b;
   not (b,B1N);
   and ( csi_opt_273 , A1 , A2 ) ;
   nor  ( UDP_IN_Y , b , csi_opt_273 ) ;
  U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
// modification by B1NB, based on SPR13943.  need to have
`ifdef functional
`else
reg csi_notifier;

        specify
    (A1 -=> Y) = (0:0:0,0:0:0);
    (A2 -=> Y) = (0:0:0,0:0:0);
    if ((!A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0);
    if ((!A1&A2)) (B1N +=> Y) = (0:0:0,0:0:0);
    if ((A1&!A2)) (B1N +=> Y) = (0:0:0,0:0:0);
        endspecify
`endif
   
endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults