scs8hs/V0.0.1/verilog/U_DFB_SETDOM_pg.v

primitive U_DFB_SETDOM_pg (Q, S, R, CK, D, VPWR, VGND);
   // same as U_DFB udp but the set line is dominant.
output Q;
input  S, R, CK, D, VPWR, VGND;
reg    Q;
  table
    0  1   ?    ?   1  0  :  ?  :  0; // Asserting reset
    0  *   ?    ?   1  0  :  0  :  0; // Changing reset
    1  ?   ?    ?   1  0  :  ?  :  1; // Asserting set (dominates reset)
    *  0   ?    ?   1  0  :  1  :  1; // Changing set
    0  ?   (01) 0   1  0  :  ?  :  0; // rising clock
    ?  0   (01) 1   1  0  :  ?  :  1; // rising clock 
    0  ?   p    0   1  0  :  0  :  0; // potential rising clock
    ?  0   p    1   1  0  :  1  :  1; // potential rising clock
    0  0   n    ?   1  0  :  ?  :  -; // Clock falling register output does not change
    0  0   ?    *   1  0  :  ?  :  -; // Changing Data
    ?  ?   ?    ?   *  0  :  ?  :  x; // any change on vpwr
    ?  ?   ?    ?   ?  *  :  ?  :  x; // any change on vgnd
 
  endtable
endprimitive
// bnb mar4,2003 - this is a modification of the verplex FF udp
// that was edited to work with tetramax and compiles
// with verilog-xl with no warnings