scs8hs/V0.0.0/verilog/scs8hs_dlxbp_1.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 


module scs8hs_dlxbp_1 ( Q , QN , D , GATE , vpwr , vgnd ) ; 
input vpwr , vgnd ; 

  output  Q , QN ; 
  input   D , GATE ; 

  wire	buf_Q , GATE_delayed , D_delayed ; 

`ifdef functional
U_DL_P_pg #0.001 ( buf_Q , D , GATE , vpwr , vgnd ) ; 
`else
    reg notifier ; 
U_DL_P_NO_pg ( buf_Q , D_delayed , GATE_delayed , notifier , vpwr , vgnd ) ; 
`endif

  buf ( Q , buf_Q ) ; 
  not ( QN , buf_Q ) ; 

`ifdef functional
`else
  wire AWAKE ; 
  assign AWAKE = ( vpwr === 1'b1 ) ; 
	specify
		 ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( D -=> QN ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    
		 ( posedge GATE => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
		 ( posedge GATE => ( QN -: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are  tris , tfall
    
		$width ( posedge GATE &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
		$width ( negedge GATE &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    
    $setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATE_delayed , D_delayed ) ; 
    $setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATE_delayed , D_delayed ) ; 
	endspecify
`endif

endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults