scs8hs/V0.0.0/verilog/scs8hs_dlclkp_4.v

`celldefine
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_dlclkp_4 ( GCLK , GATE , CLK , vpwr , vgnd ) ; 
input vpwr , vgnd ; 
  output GCLK ; 
  input  GATE , CLK ; 
  wire m0 , clkn ; 
  wire CLK_delayed , GATE_delayed ; 

`ifdef functional
  not ( clkn , CLK ) ; 
U_DL_P_pg ( m0 , GATE , clkn , vpwr , vgnd ) ; 
  and ( GCLK , m0 , CLK ) ; 

`else
  reg notifier ; 
  not ( clkn , CLK_delayed ) ; 
U_DL_P_NO_pg ( m0 , GATE_delayed , clkn , notifier , vpwr , vgnd ) ; 
  and ( GCLK , m0 , CLK_delayed ) ; 

  wire AWAKE ; 
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  specify
    ( CLK +=> GCLK ) = ( 0:0:0 , 0:0:0 ) ;                         // delays are tris , tfall
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , GATE_delayed ) ; 
    $setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , GATE_delayed ) ; 
  endspecify
`endif


endmodule
`endcelldefine
`disable_portfaults
`nosuppress_faults