scs8hs/V0.0.0/verilog/scs8hs_conb_1.v

`celldefine
// This is the vcc and vss cell.
`suppress_faults
`enable_portfaults

`ifdef TETRAMAX
`define functional
`endif

`ifdef functional
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_distributed
`endif
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_unit
`endif
`else
 `timescale 1ns / 1ps
`ifndef dont_change_delay_mode // See CDT 66389 for detail on dont_change_delay_mode
 `delay_mode_path
`endif
`endif 

module scs8hs_conb_1 (HI, LO, vpwr , vgnd );
input vpwr, vgnd;
   output HI, LO;

   pullup (UDP_IN_HI);
  U_VPWR_VGND (HI, UDP_IN_HI, vpwr, vgnd) ;
   pulldown (LO);

endmodule
`endcelldefine