s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres4v2.v

//Verilog HDL for "s8iom0s8", "s8iom0s8_top_xres4v2" "behavioral"
// ===============================================
// Copyright 2013, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
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// treaty provisions. Therefore, you must treat this software like any
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// ========================================================================================================
// File     :$File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_xres4v2/behavioral/verilog.v $
// Author   : PJPK
// Date     : July 21, 2014
// $Revision: 1 $
// ========================================================================================================
// Description : XRES (Input buffer with Glitch filter)



`timescale 1ns/1ps

module s8iom0s8_top_xres4v2 ( tie_weak_hi_h,  xres_h_n, tie_hi_esd, tie_lo_esd,
    amuxbus_a, amuxbus_b, pad, pad_a_esd_h, enable_h, en_vddio_sig_h, inp_sel_h, filt_in_h,
    disable_pullup_h, pullup_h, enable_vddio
`ifdef USE_PG_PIN    
    ,vccd, vcchib, vdda, vddio,vddio_q, vssa, vssd, vssio, vssio_q, vswitch
`endif   
     );

    output xres_h_n;
    inout amuxbus_a;
    inout amuxbus_b;
    inout pad;
    input disable_pullup_h;
    input enable_h; 
    input en_vddio_sig_h; 
    input inp_sel_h; 
    input filt_in_h;
    inout pullup_h;
    input enable_vddio;
    
`ifdef USE_PG_PIN 
    
    input vccd;
    input vcchib;
    input vdda;
    input vddio;
    input vddio_q;
    input vssa;
    input vssd;
    input vssio;
    input vssio_q;
    input vswitch;
    
    
    wire mode_vcchib;
    wire pwr_good_xres_tmp 	= (vddio===1) && (vddio_q===1) && ((mode_vcchib && enable_vddio)===1 ? vcchib===1 : 1'b1) &&  (vssio===0) && (vssd===0);
    
    wire pwr_good_xres_h_n 		= (vddio_q===1) && (vssd===0);
    
    wire pwr_good_pullup 		= (vddio===1) && (vssd===0);

`else    
    
    supply1 vccd;
    supply1 vcchib;
    supply1 vdda;
    supply1 vddio;
    supply1 vddio_q;
    supply0 vssa;
    supply0 vssd;
    supply0 vssio;
    supply0 vssio_q;
    supply1 vswitch;
    
    wire pwr_good_xres_tmp = 1;
    
    wire pwr_good_xres_h_n 	  = 1;
    
    wire pwr_good_pullup 	  = 1;
   
    
`endif
    
    inout pad_a_esd_h;
    output tie_hi_esd;
    output tie_lo_esd;
    inout tie_weak_hi_h;



wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (tie_weak_hi_h, tmp1, pwr_good_pullup===0  ? 1'bx : 1);


tran p2 (pad, pad_a_esd_h);

buf p4 (tie_hi_esd, vddio);
buf p5 (tie_lo_esd, vssio);

//====================================================================================================================================    

// Resistive pullup with disable
    
    wire tmp;
    pullup (pull1) p3 (tmp); tranif0 x_pull (pullup_h, tmp, pwr_good_pullup===0 || ^disable_pullup_h===1'bx ? 1'bx : disable_pullup_h);

   
//======================================================================================================================================   

	parameter MAX_WARNING_COUNT = 100;

`ifdef S8IOM0S8_TOP_XRES4V2_DISABLE_DELAY
	parameter MIN_DELAY = 0;
	parameter MAX_DELAY = 0;
`else
	parameter MIN_DELAY = 50;
	parameter MAX_DELAY = 600;	
`endif
	
// AC_SPEC # FOR DELAY from BROS : AC.XRESV2.1, AC.XRESV2.2  (in 001-70428_0J_HardIP_Tables -> HardIP_AC_Specs_ProdTest)


integer min_delay, max_delay;

initial begin
	min_delay = MIN_DELAY;  
	max_delay = MAX_DELAY;
end



`ifdef S8IOM0S8_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
   parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
   parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif

integer     disable_enable_vddio_change_x    = DISABLE_ENABLE_VDDIO_CHANGE_X;

//Added by JOSH for CDT#184774
reg notifier_enable_h; 


//======================================================================================================================================   

// TIMING SECTION : DELAY will be replaced by back-annotated delay values from .lib model

// NOTE : Since pad => xres_h_n path goes through RC Glitch filter, a default parameterized DELAY is tied to these delay arcs
//        This DELAY can be set to 0 by defining S8IOM0S8_TOP_XRES4V2_DISABLE_DELAY (macro) in the Testbench

specify

`ifdef S8IOM0S8_TOP_XRES4V2_DISABLE_DELAY
	specparam DELAY = 0;
`else
	specparam DELAY = 50;

`endif

   
   if (inp_sel_h==0  &  enable_h==0  & enable_vddio==0 & en_vddio_sig_h==1) (pad   => xres_h_n) =  (0:0:0 , 0:0:0);
   if (inp_sel_h==0  &  enable_h==1  & enable_vddio==1 & en_vddio_sig_h==1) (pad   => xres_h_n) =  (0:0:0 , 0:0:0);
   if (inp_sel_h==0  &  enable_h==1  & enable_vddio==1 & en_vddio_sig_h==0) (pad   => xres_h_n) =  (0:0:0 , 0:0:0);
   if (inp_sel_h==0  &  enable_h==0  & enable_vddio==0 & en_vddio_sig_h==0) (pad   => xres_h_n) =  (0:0:0 , 0:0:0);
   
   if (inp_sel_h==1) (filt_in_h => xres_h_n) =  (0:0:0 , 0:0:0);
 
//Added by JOSH for CDT#184774
    specparam tsetup = 0;
    specparam thold = 5;

  
 `ifdef functional
 `else

 $setuphold (posedge enable_vddio, posedge enable_h,     tsetup, thold,  notifier_enable_h); 
 $setuphold (negedge enable_h,     negedge enable_vddio, tsetup, thold,  notifier_enable_h); 

 `endif 
///////////////////////////////

endspecify

//==================================================================================================================================================   

//Added by JOSH for CDT#184774
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(pad or enable_h or en_vddio_sig_h or enable_vddio or inp_sel_h or filt_in_h or pwr_good_xres_tmp or disable_pullup_h or pullup_h or tie_weak_hi_h)
begin
corrupt_enable <= 1'b0;
end

///////////////////////////////

// XRES Outputs
   
    

    // INTERNAL OUTPUT : xres_tmp
    
    assign mode_vcchib 	= enable_h && !en_vddio_sig_h;
    

   wire xres_tmp 	= (pwr_good_xres_tmp===0 || ^pad===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^enable_vddio===1'bx) || (corrupt_enable===1'bx) ||

    			  (mode_vcchib===1'b1 && enable_vddio===0 && (disable_enable_vddio_change_x===0)))
        			  
			  ? 1'bx : pad;
    
 

    // OUTPUT : xres_h_n
    
    wire x_on_xres_h_n = (pwr_good_xres_h_n===0 
    
    			|| ^inp_sel_h===1'bx 
			
			|| inp_sel_h===1 && ^filt_in_h===1'bx
			
			|| inp_sel_h===0 && xres_tmp===1'bx);
			
    
     assign #1  xres_h_n = x_on_xres_h_n===1 ? 1'bx : (inp_sel_h===1 ? filt_in_h : xres_tmp);	// delay added to account for cdt172151	
			


    
    realtime t_pad_current_transition,t_pad_prev_transition;
    realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
     
     
     // Input pulse-width calculation for "pad" input
     
     realtime pad_pulse_width, filt_in_h_pulse_width;
     
     always @(pad)
     begin
     	  
	  if (^pad !== 1'bx)
	  begin
	  	t_pad_prev_transition    	= t_pad_current_transition;
	  	t_pad_current_transition 	= $realtime;
	  	pad_pulse_width 	     	= t_pad_current_transition - t_pad_prev_transition;
	  end
	  else
	  begin
	  	t_pad_prev_transition 		= 0;
		t_pad_current_transition 	= 0;
		pad_pulse_width 		= 0;
	  end
          
     end	
     
     always @(filt_in_h)
     begin
     	  
	  if (^filt_in_h !== 1'bx)
	  begin
	  	t_filt_in_h_prev_transition    			= t_filt_in_h_current_transition;
	  	t_filt_in_h_current_transition 			= $realtime;
	  	filt_in_h_pulse_width 	     			= t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
	  end
	  else
	  begin
	  	t_filt_in_h_prev_transition 			= 0;
		t_filt_in_h_current_transition 			= 0;
		filt_in_h_pulse_width 				= 0;
	  end
          
     end

//======================================================================================================================================================   

// WARNING message if input pulse width falls between min and max delay. 

reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;

initial
begin
  
  dis_err_msgs = 1'b1;
  
   
  msg_count_pad = 0; msg_count_filt_in_h = 0;
  
  `ifdef S8IOM0S8_TOP_XRES4V2_DIS_ERR_MSGS
  `else
    #1;
    dis_err_msgs = 1'b0;
  `endif
end

always @(pad_pulse_width) 
begin
  	if (!dis_err_msgs) 
  	begin
    		if (inp_sel_h===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay)) 
		begin
			
			msg_count_pad = msg_count_pad + 1;
			
			->event_errflag_pad_pulse_width;
			
			if (msg_count_pad <= MAX_WARNING_COUNT)
			begin
				$display("\n ===WARNING=== s8iom0s8_top_xres4v2 :  Width of Input pulse for pad input (= %3.2f ns)  is found to be in \
				the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \
				%m\n",pad_pulse_width,min_delay,max_delay,$stime);
			end
			else
			if (msg_count_pad == MAX_WARNING_COUNT+1)
			begin
				$display("\n ===WARNING=== s8iom0s8_top_xres4v2 :  Further WARNING messages will be suppressed as the \
				message count has exceeded 100 %m\n",$stime);
			end
		end
  	end
end

always @(filt_in_h_pulse_width) 
begin
  	if (!dis_err_msgs) 
  	begin
    		if (inp_sel_h===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay)) 
		begin
			msg_count_filt_in_h = msg_count_filt_in_h + 1;
			
			->event_errflag_filt_in_h_pulse_width;
			
			if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
			begin

				$display("\n ===WARNING=== s8iom0s8_top_xres4v2 :  Width of Input pulse for filt_in_h input (= %3.2f ns)  is found to be in \
				the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \
				%m\n",filt_in_h_pulse_width,min_delay,max_delay,$stime);
			end
			else
			if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
			begin

				$display("\n ===WARNING=== s8iom0s8_top_xres4v2 :  Further WARNING messages will be suppressed as the \
				message count has exceeded 100 %m\n",$stime);
			end
		end
  	end
end

//======================================================================================================================================   

endmodule