s8iom0s8/V0.2.1/verilog/s8iom0s8_top_xres3v2.v

// Verilog HDL for "s8iom0s8", "s8iom0s8_top_xres3v2" "behavioral"
// ===============================================
// Copyright 2011, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
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// treaty provisions. Therefore, you must treat this software like any
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// ========================================================================================================
// File     :$File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_xres3v2/behavioral/verilog.v $
// Author   : GURU
// Date     : Feb 14, 2013
// $Revision: 1 $
// ========================================================================================================
// Description : XRES (Input buffer with Glitch filter)

module s8iom0s8_top_xres3v2 (xres_h_n, xres_n, amuxbus_a, amuxbus_b, pad,
`ifdef USE_PG_PIN
	vccd, vcchib, vdda, vddio, vddio_q, vssa, vssd, vssio, vssio_q, vswitch, 
`endif
	pad_a_esd_h, tie_weak_hi_h); 
	
    output xres_h_n;
    output xres_n;
    inout amuxbus_a;
    inout amuxbus_b;
    inout pad;
`ifdef USE_PG_PIN 
    inout vccd;
    inout vcchib;
    inout vdda;
    inout vddio;
    inout vddio_q;
    inout vssa;
    inout vssd;
    inout vssio;
    inout vssio_q;
    inout vswitch;
    
    wire pwr_good_lv = (vddio===1) && (vddio_q===1) && (vcchib===1) &&  (vssio===0) && (vssd===0);
    wire pwr_good_hv = (vddio===1) && (vddio_q===1) && (vssio===0) && (vssd===0);
`else    
    supply1 vccd;
    supply1 vcchib;
    supply1 vdda;
    supply1 vddio;
    supply1 vddio_q;
    supply0 vssa;
    supply0 vssd;
    supply0 vssio;
    supply0 vssio_q;
    supply1 vswitch;
    
    wire pwr_good_lv = 1;
    wire pwr_good_hv = 1;
`endif
    
    inout pad_a_esd_h;
    inout tie_weak_hi_h;



pullup (pull1) p1 (tie_weak_hi_h);

tran p2 (pad, pad_a_esd_h);

	parameter MAX_WARNING_COUNT = 100;

`ifdef S8IOM0S8_TOP_XRES3V2_DISABLE_DELAY
	parameter MIN_DELAY = 0;
	parameter MAX_DELAY = 0;
	parameter DELAY = 0;
`else
	parameter MIN_DELAY = 50;
	parameter MAX_DELAY = 600;	
	parameter DELAY = MIN_DELAY;

`endif
	
// AC_SPEC # FOR DELAY from BROS : AC.XRESV2.1, AC.XRESV2.2  (in 001-70428_0J_HardIP_Tables -> HardIP_AC_Specs_ProdTest)


integer min_delay, max_delay;

initial begin
	min_delay = MIN_DELAY;  
	max_delay = MAX_DELAY;
end
    

//======================================================================================================================================   
// Glitch filter 
    
    wire xres_h_n,xres_n; 
    real pulse_width;
    
        
    
    assign xres_h_n = (pwr_good_hv===0 || ^pad===1'bx ) ? 1'bx : pad;
    assign xres_n   = (pwr_good_lv===0 || ^pad===1'bx ) ? 1'bx : pad;
    
    
    realtime t_current_transition,t_prev_transition;
    
     
     always @(pad)
     begin
     	  
	  if (^pad !== 1'bx)
	  begin
	  	t_prev_transition    = t_current_transition;
	  	t_current_transition = $realtime;
	  	pulse_width 	     = t_current_transition - t_prev_transition;
	  end
	  else
	  begin
	  	t_prev_transition = 0;
		t_current_transition = 0;
		pulse_width = 0;
	  end
          
     end	
     

//======================================================================================================================================   

// WARNING message if input pulse width falls between min and max delay. 

reg dis_err_msgs;
integer msg_count;


initial
begin
  dis_err_msgs = 1'b1;
  msg_count = 0;
  `ifdef S8IOM0S8_TOP_XRES3V2_DIS_ERR_MSGS
  `else
    #1;
    dis_err_msgs = 1'b0;
  `endif
end

always @(pulse_width) 
begin
  	if (!dis_err_msgs) 
  	begin
    		if (pulse_width > min_delay && pulse_width < max_delay) 
		begin
			msg_count = msg_count + 1;
			
			if (msg_count <= MAX_WARNING_COUNT)
				$display("\n ===WARNING=== s8iom0s8_top_xres3v2 :  Width of Input pulse for pad input (= %3.2f ns)  is found to be in \
				the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \
				%m\n",pulse_width,min_delay,max_delay,$stime);
			else
			if (msg_count == MAX_WARNING_COUNT+1)
				$display("\n ===WARNING=== s8iom0s8_top_xres3v2 :  Further WARNING messages will be suppressed as the \
				message count has exceeded 100 %m\n",$stime);
		end
  	end
end



//======================================================================================================================================   

// TIMING SECTION : DELAY will be replaced by back-annotated delay values from .lib model

specify

	(pad	=> xres_h_n) =  (0:0:0 , 0:0:0);
	(pad	=> xres_n)   =  (0:0:0 , 0:0:0);

endspecify


endmodule