s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp3.v

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// File     : $File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_tp3/behavioral/verilog.v $  
// Author   : guru
// Date     : $Date: 2018/04/26 12:23:52 GMT $
// $Revision: 1 $
// ===============================================
// Description:   behavioral model for s8iom0s8_corner_top_tp3
`timescale 1ns/1ps 

module s8iom0s8_top_tp3 ( tp3, tp3_out  
`ifdef USE_PG_PIN
 , vddd, vssd 
`endif
);

    
    inout tp3;
    inout tp3_out;

`ifdef USE_PG_PIN 
    inout vddd;
    inout vssd;
    wire pwr_good = (vddd===1'b1) && (vssd===1'b0);
`else
    supply1 vddd;
    supply0 vssd;
    wire pwr_good = 1'b1;
`endif

tranif1 (tp3, tp3_out, 1'b1);


endmodule