s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp2.v

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// File     : $File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_tp2/behavioral/verilog.v $ 
// Author   : rud
// Date     : $Date: 2018/04/26 12:23:52 GMT $
// $Revision: 1 $
// ===============================================
// Description:   behavioral model for s8iom0s8_top_tp2
`timescale 1ns/1ps 

module s8iom0s8_top_tp2 (tp2, tp2_out,vneg, amuxbus_a, amuxbus_b
`ifdef USE_PG_PIN    
    , vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd, vssio,
    vssd, vssio_q 
`endif
, en_tp2, tp2_div);
    
    inout tp2;
    inout tp2_out;
    inout vneg ;
    input en_tp2;
    output tp2_div;
    inout amuxbus_a;
    inout amuxbus_b;

`ifdef USE_PG_PIN
	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;
        wire pwr_good_1 = (vddio===1'b1) && (vssio===1'b0) && (vneg===1'b0);
        wire pwr_good_2 = (vccd===1'b1) && (vddio===1'b1) && (vssd===1'b0) ;
`else
	supply1 vddio;
	supply1 vddio_q;
	supply1 vdda;
	supply1 vccd;
	supply1 vswitch;
	supply1 vcchib;
	supply1 vpb;
	supply1 vpbhib;
	supply0 vssd;
	supply0 vssio;
	supply0 vssio_q;
	supply0 vssa;
        wire pwr_good_1 = 1;
        wire pwr_good_2 = 1;
`endif
    
//tp2 and tp2_out are inout type connected through resistor. Either of the pins can be driven so tranif1 has been used.
//assign tp2_out = (pwr_good_1&&pwr_good_2&&(^en_tp2!==1'bx)&&(^tp2!==1'bx))? tp2:1'bx;
//assign tp1_div = pwr_good_2 ? ( (en_tp1===1'bx )? 1'bx : (en_tp1 ? tp1_out: 1'bz ) ): 1'bx ;

wire enable;

assign enable = (pwr_good_1&&pwr_good_2) ? ((^en_tp2!==1'bx) ? 1'b1 : 1'bx) :1'bx;
assign tp2 = (^enable!==1'bx) ? 1'bz :1'bx;
assign tp2_out = (^enable!==1'bx) ? 1'bz :1'bx;
tranif1 (tp2, tp2_out, enable);

wire pwr_ip_good = pwr_good_2 && (^en_tp2!==1'bx);
wire tp2_out_valid = (^tp2_out!==1'bx);
assign tp2_div = pwr_ip_good ? (en_tp2===1 ? (tp2_out_valid ? 1'b1:1'bx) : 1'bz ) : 1'bx ; //tp2_div is never 1'b0 in a valid condition according to circuit's behaviour


endmodule