s8iom0s8/V0.2.1/verilog/s8iom0s8_top_tp1v2.v

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// File     : $File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_tp1v2/behavioral/verilog.v $  
// Author   : GURU
// Date     : $Date: 2018/05/15 18:52:16 GMT $
// $Revision: 1 $
// ===============================================
// Description:   behavioral model for s8iom0s8_top_tp1

`timescale 1ns/1ps 

module s8iom0s8_top_tp1v2 ( tp1, tp1_out, amuxbus_a, amuxbus_b
`ifdef USE_PG_PIN    
    ,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd, vssio,
    vssd, vssio_q 
`endif
 , en_tp1,tp1_div);

    
    inout tp1;
    inout tp1_out;
    inout amuxbus_a;
    inout amuxbus_b;

`ifdef USE_PG_PIN
	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;
        wire pwr_good = (vddio===1'b1) && (vssio===1'b0);
`else

	supply1 vddio;
	supply1 vddio_q;
	supply1 vdda;
	supply1 vccd;
	supply1 vswitch;
	supply1 vcchib;
	supply1 vpb;
	supply1 vpbhib;
	supply0 vssd;
	supply0 vssio;
	supply0 vssio_q;
	supply0 vssa;
        wire pwr_good = 1'b1;
`endif

    input en_tp1;
    output tp1_div ;


tranif1 x_tp1 (tp1, tp1_out, (pwr_good===1'b0 ? 1'bx : 1'b1));

bufif1 x_tp1_div (tp1_div, tp1, vssd !== 1'b0 ? 1'bx : en_tp1);




endmodule