s8iom0s8/V0.2.1/verilog/s8iom0s8_top_pwrdetv2.v

// Verilog HDL for "s8iom0s8", "s8iom0s8_top_pwrdetv2" "behavioral"
// ===============================================
// Copyright 2011, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by United States copyright laws and international
// treaty provisions. Therefore, you must treat this software like any
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//
// This software is protected by and subject to worldwide patent
// coverage, including U.S. and foreign patents. Use may be limited by
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// ========================================================================================================
// File     :$File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_pwrdetv2/behavioral/verilog.v $
// Author   : GURU
// Date     : March 21, 2013
// $Revision: 1 $
// ========================================================================================================
// Description : vddd and vddio power detectors

`timescale 1ns/1ps

module s8iom0s8_top_pwrdetv2 (out1_vddd_hv, out1_vddio_hv, out2_vddd_hv, 
           out2_vddio_hv, out3_vddd_hv, out3_vddio_hv, tie_lo_esd, 
           vddd_present_vddio_hv, vddio_present_vddd_hv, 
`ifdef USE_PG_PIN	   
	   vccd, vddd1, vddd2, vddio_q, vssa, vssd, vssio_q, 
`endif
           in1_vddd_hv, in1_vddio_hv, in2_vddd_hv, in2_vddio_hv, in3_vddd_hv, in3_vddio_hv ,rst_por_hv_n);
    output out1_vddd_hv;
    output out1_vddio_hv;
    output out2_vddd_hv;
    output out2_vddio_hv;
    output out3_vddd_hv;
    output out3_vddio_hv;
    output tie_lo_esd;
    output vddd_present_vddio_hv;
    output vddio_present_vddd_hv;
    
`ifdef USE_PG_PIN
    inout vccd;
    inout vddd1;
    inout vddd2;
    inout vddio_q;
    inout vssa;
    inout vssd;
    inout vssio_q;
`else
    supply1 vccd;
    supply1 vddd1;
    supply1 vddd2;
    supply1 vddio_q;
    supply0 vssa;
    supply0 vssd;
    supply0 vssio_q;
`endif
    input in1_vddd_hv;
    input in1_vddio_hv;
    input in2_vddd_hv;
    input in2_vddio_hv;
    input in3_vddd_hv;
    input in3_vddio_hv;
    input rst_por_hv_n;



`ifdef S8IOM0S8_TOP_PWRDETV2_DISABLE_STARTUP_DELAY
	parameter STARTUP_DELAY = 0;
`else
	parameter STARTUP_DELAY = 2000;
`endif

// AC_SPEC # FOR DELAY from BROS : AC.DET.3 and AC.DET.4  (in 001-70428_0J_HardIP_Tables -> HardIP_AC_Specs_ProdTest)


integer startup_delay;

initial startup_delay = STARTUP_DELAY;

//===================================================================================================================================================================

// 1. VDDIO_PRESENT_VDDD_HV

`ifdef USE_PG_PIN
	wire pwr_good_vddio_present_vddd_hv    	=  (vddd1===1) && (vssa===0) && (vssd===0);
						   
	wire x_on_vddio_present_vddd_hv	=  pwr_good_vddio_present_vddd_hv===0 || ^rst_por_hv_n===1'bx || ^vddio_q===1'bx; 
	
	assign vddio_present_vddd_hv 	= x_on_vddio_present_vddd_hv===1 ? 1'bx : ((rst_por_hv_n===0 && vccd===0 && vddio_q===0) ? 1'b0 : vddio_q); 

`else

	assign vddio_present_vddd_hv = ^rst_por_hv_n===1'bx ? 1'bx : 1'b1;

`endif


				
// 2. OUT1_VDDD_HV, OUT2_VDDD_HV, OUT3_VDDD_HV


assign  out1_vddd_hv	=   vddio_present_vddd_hv && in1_vddio_hv;


assign  out2_vddd_hv	=   vddio_present_vddd_hv && in2_vddio_hv;


assign  out3_vddd_hv	=   vddio_present_vddd_hv && in3_vddio_hv;


//===================================================================================================================================================================

// 3. VDDD_PRESENT_VDDIO_HV

`ifdef USE_PG_PIN
	wire pwr_good_vddd_present_vddio_hv    	=  (vddio_q===1) && (vssa===0) && (vssio_q===0);
	
	wire x_on_vddd_present_vddio_hv 	=  (pwr_good_vddd_present_vddio_hv===0) || (^vddd2===1'bx);
	
	wire vddd_present_vddio_hv_buf		=   x_on_vddd_present_vddio_hv===1 ? 1'bx : vddd2;
	
	assign #(startup_delay,startup_delay,0) vddd_present_vddio_hv	=   vddd_present_vddio_hv_buf;

`else
	assign vddd_present_vddio_hv  	=  1;
`endif



// 4. OUT1_VDDIO_HV, OUT2_VDDIO_HV, OUT3_VDDIO_HV


assign  out1_vddio_hv	=    (vddd_present_vddio_hv && in1_vddd_hv);


assign  out2_vddio_hv	=    (vddd_present_vddio_hv && in2_vddd_hv);


assign  out3_vddio_hv	=    (vddd_present_vddio_hv && in3_vddd_hv);

//===================================================================================================================================================================

// 5. TIE_LO_ESD

assign tie_lo_esd = vssd;

//===================================================================================================================================================================
// WARNING CONDITIONS


reg dis_err_msgs;

initial
begin
  dis_err_msgs = 1'b1;
  `ifdef S8IOM0S8_TOP_PWRDETV2_DIS_ERR_MSGS
  `else
    #1;
    dis_err_msgs = 1'b0;
  `endif
end

event event_warning_unreliable_output;

wire #(100) warning_unreliable_output = rst_por_hv_n===1 && vccd!==1 && vddio_q===0;

always @(warning_unreliable_output) 
begin
  if (!dis_err_msgs) 
  begin
    	if (warning_unreliable_output===1)
	begin
		$display("\n ===WARNING=== s8iom0s8_top_pwrdetv2 :  rst_por_hv_n===1 && vccd!==1 && vddio_q===0 : In this state, the vddio detector output may be unreliable: %m\n",$stime);
		->event_warning_unreliable_output;		
	end
  end
end

//=========================================================================================================================================

`ifdef functional 

`else

 specify
 	(in1_vddio_hv	=> out1_vddd_hv) =  (0:0:0 , 0:0:0);
 	(in2_vddio_hv	=> out2_vddd_hv) =  (0:0:0 , 0:0:0);
 	(in3_vddio_hv	=> out3_vddd_hv) =  (0:0:0 , 0:0:0);

	(in1_vddd_hv	=> out1_vddio_hv) =  (0:0:0 , 0:0:0);
 	(in2_vddd_hv	=> out2_vddio_hv) =  (0:0:0 , 0:0:0);
 	(in3_vddd_hv	=> out3_vddio_hv) =  (0:0:0 , 0:0:0);

	$width  (negedge rst_por_hv_n,	      (0:0:0));
 endspecify
 
`endif

 
endmodule