s8iom0s8/V0.2.1/verilog/s8iom0s8_top_power_lvc_wpad.v

//Verilog HDL for "s8iom0s8", "s8iom0s8_top_power_lvc_wpad" "behavioral"


module s8iom0s8_top_power_lvc_wpad ( p_pad, amuxbus_a, amuxbus_b
`ifdef USE_PG_PIN
  , p_core, bdy2_b2b, drn_lvc1, drn_lvc2, ogc_lvc, src_bdy_lvc1, src_bdy_lvc2, vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd, vssio, vssd, vssio_q
`endif
 );

  inout p_pad;
  inout amuxbus_a;
  inout amuxbus_b;
`ifdef USE_PG_PIN
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout ogc_lvc;
  inout drn_lvc1;
  inout bdy2_b2b;
  inout drn_lvc2;
  inout p_core;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;
`else
  supply0 src_bdy_lvc1;
  supply0 src_bdy_lvc2;
  supply1 ogc_lvc;
  supply1 drn_lvc1;
  supply1 bdy2_b2b;
  supply0 drn_lvc2;
  supply1 p_core;
  supply1 vddio;
  supply1 vddio_q;
  supply1 vdda;
  supply1 vccd;
  supply1 vswitch;
  supply1 vcchib;
  supply1 vpb;
  supply1 vpbhib;
  supply0 vssd;
  supply0 vssio;
  supply0 vssio_q;
  supply0 vssa;
`endif

	assign p_core = p_pad;

endmodule