s8iom0s8/V0.2.1/verilog/s8iom0s8_top_lvclamp.v

//Verilog HDL for "s8iom0s8", "s8iom0s8_top_lvclamp" "behavioral"


module s8iom0s8_top_lvclamp (
`ifdef USE_PG_PIN
 drn_lvc, ogc_lvc, src_bdy_lvc
`endif 
 );

`ifdef USE_PG_PIN
    inout drn_lvc;
    inout ogc_lvc;
    inout src_bdy_lvc;
`else
  supply1 ogc_lvc;
  supply1 drn_lvc;
  supply0 src_bdy_lvc;
`endif

endmodule